Frequency adjusting apparatus and dll circuit including the same

Abstract

A frequency adjusting apparatus includes a frequency control signal generating unit that generates a multi-bit frequency control signal, which is changed in level bit by bit, in response to a reference clock signal, and a frequency adjusting unit that adjusts the frequency of the reference clock signal in response to the multi-bit frequency control signal.

1 . A frequency adjusting apparatus, comprising:
 a frequency control signal generating unit configured to generate a multi-bit frequency control signal, which is changed in level bit by bit, in response to a reference clock signal; and   a frequency adjusting unit configured to adjust the frequency of the reference clock signal in response to the multi-bit frequency control signal.   
   
   
       2 . The frequency adjusting apparatus of  claim 1 , wherein the frequency control signal generating unit is configured to cyclically increase or decrease the number of high-level signals in the multi-bit frequency control signal in synchronization with the toggle timing of the reference clock signal. 
   
   
       3 . The frequency adjusting apparatus of  claim 2 , wherein the frequency control signal generating unit includes:
 a shift section configured to shift an inverted feedback signal and the multi-bit frequency control signal in response to a reset signal and the reference clock signal, and to adjust the logical value of the multi-bit frequency control signal; and   an inverting section configured to invert one bit of the multi-bit frequency control signal and output the inverted bit as the inverted feedback signal.   
   
   
       4 . The frequency adjusting apparatus of  claim 2 , wherein the frequency adjusting unit is configured to cyclically increase or decrease a delay time to be applied to the reference clock signal according to a cyclical change in the logical value of the frequency control signal. 
   
   
       5 . The frequency adjusting apparatus of  claim 4 , wherein the frequency adjusting unit includes:
 a driving section configured to drive the reference clock signal to generate the frequency-adjusted clock signal; and   a delay section configured to delay the operation of the driving section in response to the multi-bit frequency control signal.   
   
   
       6 . The frequency adjusting apparatus of  claim 1 , further comprising a clock signal dividing unit configured to divide the frequency of the reference clock signal to generate a divided clock signal. 
   
   
       7 . The frequency adjusting apparatus of  claim 6 , wherein the clock signal dividing unit includes:
 a divided clock signal generating section generate a plurality of divided clock signals having different division ratios from the reference clock signal in response to a reset signal; and   a switching section configured to select one of the reference clock signals and the plurality of divided clock signals in response to a selection signal, and output the selected clock signal as the reference clock signal.   
   
   
       8 . The frequency adjusting apparatus of  claim 7 , wherein the selection signal is implemented by a test signal during a test operation, and if the test operation ends, is implemented by a signal whose level is fixed by a mode register or a fuse circuit. 
   
   
       9 . A frequency adjusting apparatus, comprising:
 a frequency control signal generating unit configured to divide the frequency of a reference clock signal by a plurality of division ratios, thereby generating a multi-bit frequency control signal; and   a frequency adjusting unit configured to adjust the frequency of the reference clock signal in response to the multi-bit frequency control signal.   
   
   
       10 . The frequency adjusting apparatus of  claim 9 , wherein the frequency control signal generating unit is configured to generate the multi-bit frequency control signal, which is cyclically changed in logical value bit by bit, in response to the reference clock signal. 
   
   
       11 . The frequency adjusting apparatus of  claim 10 , wherein the frequency control signal generating unit includes:
 a first dividing section configured to divide-by-one the reference clock signal in response to a reset signal to generate a first frequency control signal; and   a second dividing section configured to divide-by-two the first frequency control signal in response to the reset signal to generate a second frequency control signal.   
   
   
       12 . The frequency adjusting apparatus of  claim 10 , wherein the frequency adjusting unit is configured to cyclically increase or decrease a delay time to be applied to the reference clock signal according to a cyclical change in the logical value of the frequency control signal. 
   
   
       13 . The frequency adjusting apparatus of  claim 12 , wherein the frequency adjusting unit includes:
 a switching section configured to, selectively invert the remaining bits of the multi-bit frequency control signal in response to the uppermost bit of the multi-bit frequency control signal and output the frequency control signal or a negative frequency control signal; and   a delay section configured to delay the reference clock signal in response to the frequency control signal or the negative frequency control signal.   
   
   
       14 . A frequency adjusting method, comprising:
 dividing a frequency of a reference clock signal by a predetermined ratio, thereby generating a divided clock signal;   cyclically changing the logical value of a multi-bit frequency control signal in response to the divided clock signal; and   applying a delay time corresponding to the logical value of the multi-bit frequency control signal to the reference clock signal.   
   
   
       15 . The frequency adjusting method of  claim 14 , wherein generating the divided clock signal includes:
 generating a plurality of divided clock signals having different division ratios from the reference clock signal in response to a reset signal; and   selecting and outputting one of the reference clock signals and the plurality of divided clock signals in response to a selection signal.   
   
   
       16 . The frequency adjusting method of  claim 15 , wherein the selection signal is implemented by a test signal during a test operation, and if the test operation ends, is implemented by a signal whose level is fixed by a mode register or a fuse circuit. 
   
   
       17 . The frequency adjusting method of  claim 14 , wherein changing the logical value of the multi-bit frequency control signal includes:
 inverting one bit of the multi-bit frequency control signal and outputting the inverted bit as an inverted feedback signal; and   shifting the inverted feedback signal and the multi-bit frequency control signal in response to a reset signal and the divided clock signal, and adjusting the logical value of the multi-bit frequency control signal.   
   
   
       18 . A DLL (Delay Locked Loop) circuit, comprising:
 a frequency adjusting apparatus configured to cyclically increase or decrease the frequency of a reference clock signal, thereby generating a frequency-adjusted clock signal;   a delay apparatus configured to delay the frequency-adjusted clock signal in response to a delay control signal, thereby generating a delayed clock signal;   a delay compensating apparatus configured to apply a delay time, which is obtained by modeling a delay amount on an output path of the delayed clock signal, to the delayed clock signal, thereby generating a feedback clock signal;   a phase comparing apparatus configured to compare the phase of the reference clock signal with the phase of the feedback clock signal, thereby generating a phase comparison signal; and   a delay control apparatus configured to generate the delay control signal in response to the phase comparison signal.   
   
   
       19 . The DLL circuit of  claim 18 , wherein the frequency adjusting apparatus includes:
 a clock signal dividing unit configured to divide the frequency of the reference clock signal to generate a divided clock signal;   a frequency control signal generating unit configured to generate a multi-bit frequency control signal, which is changed in level bit by bit, in response to the divided clock signal; and   a frequency adjusting unit configured to adjust the frequency of the reference clock signal in response to the multi-bit frequency control signal and generate the frequency-adjusted clock signal.   
   
   
       20 . The DLL circuit of  claim 19 , wherein the frequency control signal generating unit is configured to cyclically increase or decrease the number of high-level signals in the multi-bit frequency control signal in synchronization with the toggle timing of the divided clock signal. 
   
   
       21 . The DLL circuit of  claim 19 , wherein the frequency adjusting unit cyclically is configured to increase or decrease a delay time to be applied to the reference clock signal according to a cyclical change in the logical value of the frequency control signal. 
   
   
       22 . The DLL circuit of  claim 18 , wherein the frequency adjusting apparatus includes:
 a frequency control signal generating unit configured to divide the frequency of the reference clock signal by a plurality of division ratios to generate a multi-bit frequency control signal; and   a frequency adjusting unit configured to adjust the frequency of the reference clock signal in response to the multi-bit frequency control signal.   
   
   
       23 . The DLL circuit of  claim 22 , wherein the frequency control signal generating unit is configured to generate the multi-bit frequency control signal, which is cyclically changed in logical value bit by bit, in response to the reference clock signal. 
   
   
       24 . The DLL circuit of  claim 22 , wherein the frequency adjusting unit cyclically is configured to increase or decrease a delay time to be applied to the reference clock signal according to a cyclical change in the logical value of the frequency control signal. 
   
   
       25 . The DLL circuit of  claim 18 , further comprising a clock signal input buffer configured to buffer an external clock signal and generate the reference clock signal.