Semiconductor Devices Including Transistors Having Three Dimensional Channels

Abstract

Semiconductor devices including a gate electrode crossing over a semiconductor fin on a semiconductor substrate are provided. A gate insulating layer is provided between the gate electrode and the semiconductor fin. A channel region having a three-dimensional structure defined at the semiconductor fin under the gate electrode is also provided. Doped region is provided in the semiconductor fin at either side of the gate electrode and an interlayer insulating layer is provided on a surface of the semiconductor substrate. A connector region is coupled to the doped region and provided in an opening, which penetrates the interlayer insulating layer. A recess region is provided in the doped region and is coupled to the connector region. The connector region contacts an inner surface of the recess region. Related methods of fabricating semiconductor devices are also provided herein.

1 . A semiconductor device comprising:
 a gate electrode crossing over a semiconductor fin on a semiconductor substrate;   a gate insulating layer between the gate electrode and the semiconductor fin;   a channel region having a three-dimensional structure defined at the semiconductor fin under the gate electrode;   a doped region formed in the semiconductor fin at either side of the gate electrode;   an interlayer insulating layer on a surface of the semiconductor substrate; and   a connector region coupled to the doped region and in an opening which penetrates the interlayer insulating layer, wherein a recess region is provided in the doped region and is coupled to the connector region and wherein the connector region contacts an inner surface of the recess region.   
   
   
       2 . The device of  claim 1 , wherein the recess region comprises a recessed region in a central portion of an upper surface of the doped region, the inner surfaces of the recess region being provided by the doped region and wherein the opening exposes at least a portion of the recess region. 
   
   
       3 . The device of  claim 1 , wherein the recess region is provided in a portion of the doped region exposed by the opening, an inner surface of the recess region and an inner surface of the opening being aligned and wherein the connector region is provided in the opening and the recess region. 
   
   
       4 . The device of  claim 1 , wherein the opening is hole-shaped and the connector region is pillar-shaped such that the connector region fills the opening. 
   
   
       5 . The device of  claim 5 , wherein the opening has a groove-shape in other words parallel to the gate electrode and the connector region has a line-shape such that it fills the opening. 
   
   
       6 . The device of  claim 1 , further comprising:
 a floating gate between the gate electrode and the gate insulating layer; and   a blocking insulating pattern between the floating gate and the gate electrode.   
   
   
       7 . The device of  claim 1 , wherein the channel region includes a recessed channel region in a central portion of an upper surface of the channel region and wherein the gate electrode is provided in the channel recess region such that the gate insulating layer is between the channel recess region and the gate electrode. 
   
   
       8 . A semiconductor device comprising:
 a gate electrode crossing over a semiconductor fin on a semiconductor substrate;   a gate insulating layer between the gate electrode and the semiconductor fin;   a channel region having a three-dimensional structure defined at the semiconductor fin under the gate electrode;   a doped region formed in the semiconductor fin at either side of the gate electrode;   an interlayer insulating layer on a surface of the semiconductor substrate; and   a connector region filling an opening, wherein the opening penetrates the interlayer insulating layer to expose at least a portion of an upper surface and both side surfaces of the doped region.   
   
   
       9 . The device of  claim 8 , wherein the opening is hole-shaped such that it has a greater width than a width of the doped region parallel to a channel width of the channel region and wherein the connector region is pillar-shaped such that it fills the opening. 
   
   
       10 . The device of  claim 8 , wherein the opening is groove-shaped such that it crosses over the doped region parallel to the gate electrode and wherein the connector region is line-shaped such that it fills the opening. 
   
   
       11 . The device of  claim 8 , further comprising:
 a floating gate between the gate electrode and the gate insulating layer; and   a blocking insulating pattern between the floating gate and the gate electrode.   
   
   
       12 . The device of  claim 8 , wherein the channel region includes a channel recess region in a central portion of an upper surface of the channel region and wherein the gate electrode fills the channel recess region such that the gate insulating layer is between the channel recess region and the gate electrode.