Method and Apparatus for Synthesis of Multimode X-Tolerant Compressor

Abstract

Methods and apparatuses for synthesizing a multimode x-tolerant compressor are described.

1 . A method of compressing test responses of a circuit under test, the circuit under test including a plurality of scan chains which includes a plurality of known scan chains and a plurality of unknown scan chains, the method comprising:
 synthesizing a compressor circuit of the circuit under test according to a selection from a plurality of compressor design strategies, the plurality of compressor design strategies having a varying sensitivity to a quantity of unknown values appearing in the test responses of the circuit under test; and the compressor circuit being synthesized selectively compressing the test responses from a plurality of groups of scan chains and a plurality of shift cycles by at least mapping the plurality of scan chains into a plurality of outputs, mapping the plurality of scan chains into the plurality of groups of scan chains, and mapping the plurality of scan chains into a plurality of modes.   
   
   
       2 . The method of  claim 1 , wherein one of the plurality of compressor design strategies includes:
 synthesizing the compressor circuit to include a plurality of configurations, wherein each configuration of the plurality of configurations is associated with a set of modes of the plurality of modes and specifies a mapping of a subset of said groups of scan chains into the plurality of scan chains.   
   
   
       3 . The method of  claim 1 , wherein one of the plurality of compressor design strategies includes:
 synthesizing the compressor circuit to include a plurality of configurations, wherein each configuration of the plurality of configurations is associated with a set of modes of the plurality of modes and specifies a mapping of the plurality of scan chains into the plurality of outputs.   
   
   
       4 . The method of  claim 1 , wherein one of the plurality of compressor design strategies includes:
 synthesizing the compressor circuit to receive a mode selection via one or more test protocols during testing, wherein the mode selection includes a set of available modes of the plurality of modes for each test protocol and includes a partition on said set of available modes into one or more subsets of compatible modes appearing in the plurality of shift cycles of each test pattern generated based on each test protocol.   
   
   
       5 . The method of  claim 1 , wherein one of the plurality of compressor design strategies includes:
 synthesizing the compressor circuit to include fully combinational control to increase the degree of freedom for a mode selection during testing, wherein the mode selection includes a set of available modes of the plurality of modes for each test protocol and includes a partition on said set of available modes into one or more subsets of compatible modes appearing in the plurality of shift cycles of each test pattern generated based on each test protocol.   
   
   
       6 . The method of  claim 1 , wherein one of the plurality of compressor design strategies includes:
 synthesizing the compressor circuit to specify a mode of the plurality of modes wherein the test responses coming from all scan chains of the plurality of scan chains are selected for compression.   
   
   
       7 . The method of  claim 1 , wherein one of the plurality of compressor design strategies includes:
 synthesizing the compressor circuit to specify a mode of the plurality of modes wherein no test responses coming from any scan chains of the plurality of scan chains are selected for compression.   
   
   
       8 . The method of  claim 1 , wherein one of the plurality of compressor design strategies includes:
 synthesizing the compressor circuit to map the plurality of scan chains into at least two groups of scan chains and to map the plurality of known scan chains into a set of known groups, such that for each known group of the set of known groups, when at least one unknown value in test responses from said each known group exists, an error in test responses from said each known group is detectable by analyzing a compressed representation of the test responses,   wherein the error and said at least one unknown value occur in a same shift cycle of the plurality of shift cycles.   
   
   
       9 . The method of  claim 1 , wherein one of the plurality of compressor design strategies includes:
 synthesizing the compressor circuit to map the plurality of scan chains into at least two groups of scan chains and to map the plurality of known scan chains into a set of known groups, such that for each known group of the set of known groups, when at least two unknown values in test responses from said each known group exist, an error in test responses from said each known group is detectable by analyzing a compressed representation of the test responses,   wherein the error and said at least two unknown values occur in a same shift cycle of the plurality of shift cycles.   
   
   
       10 . The method of  claim 1 , wherein one of the plurality of compressor design strategies includes:
 synthesizing the compressor circuit to map the plurality of known scan chains into a set of known groups, such that for each known group of the set of known groups, an error in test responses from said each known group is detectable by analyzing a compressed representation of the test responses, regardless of two unknown values in test responses from any said each known group,   wherein the error and said two unknown values occur in a same shift cycle of the plurality of shift cycles, and wherein the error and said two unknown values occur in a set of scan chains of the plurality of known scan chains, and   wherein the set of scan chains is in a same clock domain.   
   
   
       11 . The method of  claim 1 , wherein one of the plurality of compressor design strategies includes:
 synthesizing the compressor circuit to map the plurality of scan chains into at least two groups of scan chains and to map the plurality of unknown scan chains into a set of unknown groups, such that for each unknown group of the set of unknown groups, an error in test responses from said each unknown group is detectable by analyzing a compressed representation of the test responses, regardless of any unknown values in test responses from said each unknown group,   wherein the error and said any unknown values occur in a same shift cycle of the plurality of shift cycles.   
   
   
       12 . The method of  claim 1 , wherein one of the plurality of compressor design strategies includes:
 synthesizing the compressor circuit to map the plurality of unknown scan chains into a set of unknown groups, such that for each unknown group of said set of unknown groups, an error in test responses from said each unknown group is detectable by analyzing a compressed representation of the test responses, regardless of any unknown values in test responses from said each unknown group,   wherein the error and said any unknown values occur in a same shift cycle of the plurality of shift cycles, and wherein the error and said any unknown values occur in a set of scan chains of the plurality of unknown scan chains, and   wherein the set of scan chains is in a same clock domain.   
   
   
       13 . The method of  claim 1 , wherein one of the plurality of compressor design strategies includes:
 mapping the plurality of scan chains into the plurality of modes having at least three mode types, including:
 primary modes associated with one group of scan chains of the plurality of groups of scan chains; 
 expanding modes associated with a union of two or more groups of scan chains of the plurality of groups of scan chains; and 
 shrinking modes associated with an intersection of two or more groups of scan chains of the plurality of groups of scan chains. 
   
   
   
       14 . The method of  claim 1 , further comprising:
 during testing, generating a subset of test patterns to detect a set of faults in the circuit under test targeting fault detection in a set of more restrictive modes of the plurality of modes wherein no more than one group of scan chains is selected for compression in each of the more restrictive modes;   identifying positions of unknown values in the test responses by simulating the subset of the test patterns; and   selecting a mode of the plurality of modes to detect any single error in test responses in one shift cycle of the plurality of shift cycles targeting fault detection in a set of less restrictive modes of the plurality of modes wherein one or more groups of scan chains are selected for compression in each of the less restrictive modes.   
   
   
       15 . The method of  claim 1 , further comprising:
 during testing, generating a subset of test patterns to detect a set of faults in the circuit under test by observing a set of test responses of interest;   identifying positions of unknown values in the test responses by simulating the subset of the test patterns; and   selecting a mode of the plurality of modes to detect an error in the set of test responses in one shift cycle.   
   
   
       16 . The method of  claim 15 , further comprising:
 suspending clock pulses of a first set of scan chains of the plurality of scan chains in a first set of clock domains to increase the error detection capability in a second set of the plurality of scan chains of the plurality of scan chains in a second set of clock domains.   
   
   
       17 . The method of  claim 1 , wherein the selection is by a user. 
   
   
       18 . wherein the selection is autonomous. 
   
   
       19 . A computer readable medium, comprising:
 computer instructions to perform a method of compressing test responses of a circuit under test, the circuit under test including a plurality of scan chains which includes a plurality of known scan chains and a plurality of unknown scan chains, the method comprising:
 synthesizing a compressor circuit of the circuit under test according to a selection from a plurality of compressor design strategies, the plurality of compressor design strategies having a varying sensitivity to a quantity of unknown values appearing in the test responses of the circuit under test; and the compressor circuit being synthesized selectively compressing the test responses from a plurality of groups of scan chains and a plurality of shift cycles by at least mapping the plurality of scan chains into a plurality of outputs, mapping the plurality of scan chains into the plurality of groups of scan chains, and mapping the plurality of scan chains into a plurality of modes. 
   
   
   
       20 . A computer apparatus, comprising:
 a computer to perform a method of compressing test responses of a circuit under test, the circuit under test including a plurality of scan chains which includes a plurality of known scan chains and a plurality of unknown scan chains, the method comprising:
 synthesizing a compressor circuit of the circuit under test according to a selection from a plurality of compressor design strategies, the plurality of compressor design strategies having a varying sensitivity to a quantity of unknown values appearing in the test responses of the circuit under test; and the compressor circuit being synthesized selectively compressing the test responses from a plurality of groups of scan chains and a plurality of shift cycles by at least mapping the plurality of scan chains into a plurality of outputs, mapping the plurality of scan chains into the plurality of groups of scan chains, and mapping the plurality of scan chains into a plurality of modes.