Processor for simultaneously executing multiple conditional execution instruction groups

Abstract

A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a code block specified by the conditional execution instruction. In one embodiment, the processor includes multiple registers for storing marking data pertaining to a number of instructions in each of multiple execution pipeline stages. In another embodiment, the processor includes write enable logic and an execution unit. The write enable logic produces write enable signals dependent upon received attributes, and the execution unit saves results of instructions of conditional execution instruction groups dependent upon the write enable signals.

1 . A processor, comprising:
 a plurality of registers for storing marking data pertaining to a number of instructions in each of a plurality of stages of an execution pipeline implemented within the processor, wherein the marking data for a given one of the instructions indicates whether the instruction is an instruction of a conditional execution instruction group.   
   
   
       2 . The processor as recited in  claim 1 , wherein the conditional execution instruction group comprises a conditional execution instruction and a code block specified by the conditional execution instruction, and wherein the code block comprises at least one instruction. 
   
   
       3 . The processor as recited in  claim 2 , wherein the conditional execution instruction specifies a condition, and wherein a result of each of the at least one instruction of the code block is saved dependent upon the existence of the specified condition in the processor during execution of the conditional execution instruction. 
   
   
       4 . The processor as recited in  claim 1 , wherein the registers are arranged as a number of register sets, wherein each register set corresponds to a different one of the stages of the execution pipeline and comprises a number of registers equal to a maximum number of instructions that may be grouped together for simultaneous execution within the processor. 
   
   
       5 . The processor as recited in  claim 4 , wherein the stages of the an execution pipeline form a series, and wherein each register of each of the register sets is coupled to provide stored marking data to a corresponding register of a register set corresponding to a subsequent stage of the execution pipeline. 
   
   
       6 . The processor as recited in  claim 1 , wherein the marking data for the given one of the instructions indicates that the instruction is either: not an instruction of the conditional execution instruction group, a first instruction of the conditional execution instruction group, a last instruction of the conditional execution instruction group, or an instruction of the conditional execution instruction group. 
   
   
       7 . A processor, comprising:
 write enable logic coupled to receive an attribute of each of a plurality of conditional execution instruction groups and configured to produce a plurality of write enable signals, wherein the attribute of each of the conditional execution instruction groups comprises a value indicative of a condition specified by a conditional execution instruction of the conditional execution instruction group; and   an execution unit coupled to receive the write enable signals and configured to save a result of at least one instruction of each of the conditional execution instruction groups dependent upon the write enable signals.   
   
   
       8 . The processor as recited in  claim 7 , wherein each of the conditional execution instruction groups comprises a conditional execution instruction and a code block specified by the conditional execution instruction, wherein the code block comprises at least one instruction. 
   
   
       9 . The processor as recited in  claim 7 , wherein each of the write enable signals corresponds to a different one of the conditional execution instruction groups and is indicative of the existence of the condition specified by the conditional execution instruction of the corresponding conditional execution instruction group.