Method of fabricating opening and plug
Abstract
A method of fabricating an opening or plug is provided. In the process of forming the opening, before a photoresist layer is formed over a dielectric layer, a treatment process is performed to form a film on the dielectric layer, wherein the film can suppress the outgasing phenomenon of the dielectric layer and prevent the later formed photoresist layer from reacting with the running-off composition component from the dielectric layer. Therefore, the problem of incomplete development due to outgasing of the dielectric layer can be solved. Additionally, in the procedure for forming a plug, before a block layer is forming on a surface of a via, a treatment process is performed to form a film on the surface of the via. Therefore, the problem of having defects inside the block layer caused by outgasing of the dielectric layer can be overcome.
Claims
exact text as granted — not AI-modified1 . A method of manufacturing a plug, comprising:
forming a patterned dielectric layer over a first conductive layer, wherein the patterned dielectric layer possesses an opening exposing a portion of the first conductive layer; performing a treatment process on a surface of the patterned dielectric layer to form a film, wherein the treatment process is an ion implantation process, the film is formed by damaging a portion of the patterned dielectric layer and protects the patterned dielectric layer from running off a plurality of composition components, and dopants used in the ion implantation process comprise boron, boron fluoride, phosphine, arsenic, aluminum, or fluoride; forming a block layer on a surface of the opening; and forming a second conductive layer in the opening.
2 . The method of claim 1 , wherein the thickness of the film is less than 1000 angstroms.
3 . The method of claim 1 , wherein the dosage of the dopants used in the ion implantation process is of about 10 14 -10 16 atoms/cm 2 .
4 . The method of claim 1 , wherein the energy for performing the ion implantation process is of about 80-120 KeV.
5 . The method of claim 1 , wherein the patterned dielectric layer is made of the material with relatively low dielectric constant or fluorine-containing glass.
6 . The method of claim 1 , wherein the opening is constructed by a via and a trench, and the trench is located over the via.Join the waitlist — get patent alerts
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