Bias generator providing for low power, self-biased delay element and delay line

Abstract

An improved bias generator incorporates a reference voltage and/or a reference current into the generation of bias voltages. In some cases, the output of a biased delay element has a constant voltage swing. A delay line of such constant output voltage swing delay elements may be shown to provide reduced power consumption compared to some known self-biased delay lines. Furthermore, in other cases, careful selection of parameters for providing the reference voltage and/or providing the reference current to a novel bias generator allows a delay line of delay elements biased by such a novel bias generator to show reduced sensitivity to operating conditions, reduced sensitivity to variation in process parameters and improved signal quality, thereby providing more robust operation.

1 . A bias generator for biasing delay elements in a delay line employing one or more delay elements, said bias generator comprising:
 a bias generator variable resistance load element, said bias generator variable resistance load element connected between a power supply voltage and a given node;   a voltage-controlled current source for generating a reference current;   a current mirror formed of a first side and a second side, said first side connected to said voltage-controlled current source so that current in said first side and current in said second side is established based on said reference current;   a reference voltage generator for generating a reference voltage; and   an operational amplifier with a non-inverting input connected to said given node, an inverting input connected to said reference voltage generator to receive said reference voltage and an output connected to control current in said bias generator variable resistance load element, wherein said operational amplifier adjusts said output to minimize a difference between voltage levels at said non-inverting input and said inverting input.   
     
     
         2 . The bias generator of  claim 1  further comprising an intermediate field effect transistor (FET), having a drain connected to said given node and a gate connected to said power supply voltage, configured so that a current through said intermediate FET includes said current in said second side of said current mirror. 
     
     
         3 . The bias generator of  claim 1  wherein said reference voltage generator is configured to generate said reference voltage such that said reference voltage is invariant in response to variations in operating conditions and variations in process parameters. 
     
     
         4 . The bias generator of  claim 1  wherein said reference voltage generator is configured to generate said reference voltage such that said reference voltage has a predetermined dependence on operating conditions. 
     
     
         5 . The bias generator of  claim 4  wherein said operating conditions include an ambient temperature. 
     
     
         6 . The bias generator of  claim 4  wherein said operating conditions include a level of said power supply voltage. 
     
     
         7 . The bias generator of  claim 1  wherein said reference voltage generator is configured to generate said reference voltage such that said reference voltage has a predetermined dependence on process parameters. 
     
     
         8 . At a bias generator, a method of controlling delay in delay elements in a delay line employing one or more delay elements, said method comprising:
 while maintaining a constant alternating current voltage swing between a differential pair of output nodes of a given delay element,   varying a first bias voltage, said first bias voltage controlling a rate at which a first output node of said differential pair of output nodes may charge; and   simultaneously varying a second bias voltage, in a manner inverse to a manner in which said first bias voltage is varied, said second bias voltage controlling a rate at which a second output node of said differential pair of output nodes may discharge.   
     
     
         9 . The method of  claim 8  further comprising:
 at a reference voltage generator, generating a reference voltage; and   said varying said second bias voltage includes adjusting said second bias voltage to maintain a given node in said bias generator at said reference voltage.   
     
     
         10 . The method of  claim 9  further comprising:
 receiving a control voltage; and   basing said varying said first bias voltage on variation in said control voltage.   
     
     
         11 . The method of  claim 10  further comprising selecting said reference voltage generator based on a pre-determined dependence of said reference voltage on an operating condition, to obtain a desired quality in a delay vs. control voltage characteristic that describes operation of said delay element. 
     
     
         12 . The method of  claim 11  wherein said operating condition is ambient temperature. 
     
     
         13 . The method of  claim 11  wherein said operating condition is power supply voltage. 
     
     
         14 . The method of  claim 11  wherein said quality is a control voltage range of said delay vs. control voltage characteristic. 
     
     
         15 . The method of  claim 11  wherein said quality is a value for a characteristic slope of said delay vs. control voltage characteristic. 
     
     
         16 . The method of  claim 10  further comprising selecting said reference voltage generator based on a pre-determined dependence of said reference voltage on a process parameter, to obtain a desired quality in a delay vs. control voltage characteristic that describes operation of said delay element. 
     
     
         17 . A bias generator for biasing delay elements in a delay line employing one or more delay elements, said bias generator comprising:
 a bias generator variable resistance load element, said bias generator variable resistance load element connected between a power supply voltage and a given node;   a voltage-controlled current source for generating a reference current, said voltage-controlled current source formed of a reference current generator supplying a reference current to a differential pair of field effect transistors (FETs), where division of said reference current between said pair of FETs is based on a reference voltage on a first branch and a control voltage on a second branch; and   a first current mirror formed of a first side and a second side, said first side connected to said voltage-controlled current source so that current in said first side and current in said second side are established based on said division of said reference current.   
     
     
         18 . The bias generator of  claim 17  further comprising an intermediate FET, having a drain connected to said given node and a gate connected to said power supply voltage, configured so that a current through intermediate FET includes said current in said second side of said current mirror. 
     
     
         19 . The bias generator of  claim 17  wherein said bias generator variable resistance load element is formed as a current mirror. 
     
     
         20 . The bias generator of  claim 17  wherein said reference current generator is configured to generate said reference current such that said reference current is invariant in response to variations in operating conditions and variations in process parameters. 
     
     
         21 . The bias generator of  claim 17  wherein said reference current generator is configured to generate said reference current such that said reference current has a predetermined dependence on operating conditions. 
     
     
         22 . The bias generator of  claim 21  wherein said operating conditions include an ambient temperature. 
     
     
         23 . The bias generator of  claim 21  wherein said operating conditions include a level of said power supply voltage. 
     
     
         24 . The bias generator of  claim 17  wherein said reference current generator is configured to generate said reference current such that said reference current has a predetermined dependence on process parameters. 
     
     
         25 . A self-biased delay element comprising:
 a reference voltage generator for generating a reference voltage;   a bias generator coupled to said reference voltage generator to receive said reference voltage, said bias generator further receiving a control voltage and generating, based on said control voltage and said reference voltage, a first bias signal and a second bias signal; and   an element arranged to receive a differential input and generate a differential output, where said differential output lags said differential input by a delay, said element arranged to receive said first bias signal and said second bias signal and base said delay on said first bias signal and said second bias signal.   
     
     
         26 . The self-biased delay element of  claim 25  wherein said differential output has a constant voltage swing. 
     
     
         27 . A self-biased delay line comprising:
 said self-biased delay element of  claim 25 , wherein said element is a first element and said differential output is a first differential output;   a second element arranged to receive said first differential output and generate a second differential output, where said second differential output lags said first differential output by said delay, said second element arranged to receive said first bias signal and said second bias signal and base said delay on said first bias signal and said second bias signal.   
     
     
         28 . An apparatus for aligning a reference signal having a reference phase with a feedback signal having a feedback phase, comprising:
 a phase comparator for comparing said reference phase and said feedback phase and for generating a phase comparator output signal that is proportional to a difference between said reference phase and feedback phase;   a charge pump coupled to said phase comparator for generating a delay control voltage in response to said phase comparator output signal;   a reference voltage generator for generating a reference voltage;   a bias generator coupled to said loop filter for receiving said reference voltage and for generating, based on said delay control voltage:
 a first bias signal with a fixed relationship to said reference voltage; and 
 a second bias signal with an inverse relationship to said first bias signal; and 
   a voltage-controlled element for receiving said reference signal and for generating said feedback signal having said feedback phase substantially aligned with said reference phase, wherein said first bias signal is configured to generate a first bias current in a first component of said voltage-controlled element and said second bias signal is configured to generate a second bias current in a second component of said voltage-controlled element.