Semiconductor integrated circuit, layout design method of semiconductor integrated circuit, and layout program product for same

Abstract

A semiconductor integrated circuit includes multiple cells each containing transistors. The transistors include a gate and diffusion layers. The multiple cells are adjacently formed in a first direction perpendicular to the gate. The distance between the cell border and the adjacent and corresponding diffusion layer, the first direction, is the same.

1 . A semiconductor integrated circuit, comprising:
 a plurality of first cells each including a first circuit and a first transistor having a first gate extending in a first direction and a plurality of first diffusion layers so that said first gate is arranged between said diffusion layers; and   a plurality of second cells each including a second circuit different from said first circuit, and a second transistor having a second gate extending in said first direction and a plurality of second diffusion layers, said second gate being arranged between said second diffusions layers,   wherein a distance between adjacent diffusion layers of first and second cells adjacently arranged among said first and second cells, in a second direction perpendicular to the first direction, and a distance between adjacent diffusion layers of first cells adjacently arranged among said first and second cells, in said second direction.   
     
     
         2 . The semiconductor integrated circuit according to  claim 1 ,
 wherein said first circuit comprises an inverter circuit, and said second circuit comprises a NAND circuit.   
     
     
         3 . A layout design method of a semiconductor integrated circuit, comprising:
 providing a cell library containing a plurality of types of cells with respectively different circuits, each of said plurality of types of cells including a plurality of diffusion layers and a gate formed in a cell border thereof, said gate extending in a first direction, and at least one of a distance from an edge of the diffusion layer to an edge of the corresponding and adjacent cell border and a distance from the gate to the edge of the corresponding and adjacent cell border, in a second direction perpendicular to the first direction, being substantially equal; and   arranging said plurality of type of cells in said first direction so that respective distances between the adjacent cell borders are substantially same with each other in the second direction.   
     
     
         4 . The layout design method according to  claim 3 , further comprising:
 providing said gates of said plurality of types of cells so that the distances from the cell border to an edge of the corresponding and adjacent gate in the second direction are substantially equal; and   arranging said plurality of type of cells in said first direction so that respective distances between the adjacent cell borders are substantially same with each other in the second direction, thereby the distance between gates of the adjacent cells being substantially equal with each other in said second direction.   
     
     
         5 . A layout design method of a semiconductor integrated circuit, comprising:
 (A) providing a cell layout including a cell having a gate extending in a first direction and first and second diffusion layers so that said gate is arranged between said first and second diffusion layers, said cell having a first distance between a first boundary of said cell and said first diffusion layer in a second direction perpendicular to the first direction, and a second distance between a second boundary of said cell and said second diffusion layer, said first and second distances being set to a limit value;   (B) generating a library data of said cell for a placement and routing tool, based on said cell layout; and   (C) recording the library data onto a storage device.   
     
     
         6 . The layout design method according to  claim 5 , further comprising:
 (D) setting a layout of a semiconductor chip by arranging the cell in said second direction, using said library data; and   (E) displaying the layout of said semiconductor chip on a display.   
     
     
         7 . The layout design method according to  claim 5 ,
 wherein the step (A) further comprises:
 extracting a layout data of diffusion layers corresponding to said first and second diffusion layers from a layout data for a cell having already being designed; and 
 changing said layout data of diffusion layers to set said first and second distances to said limit value. 
   
     
     
         8 . The layout design method according to  claim 5 , further comprising:
 (F) setting the cell layout by substantially equalizing the distance between a gate and an adjacent cell boundary in said second direction, to said limit value.   
     
     
         9 . A layout program product for a semiconductor integrated circuit according to  claim 5  for executing the layout design method for semiconductor integrated circuits on a computer. 
     
     
         10 . A layout program product storing a program to produce a layout design of a semiconductor integrated circuit, comprising:
 reading a library data including a cell which has a first diffusion layer and a second diffusion layer formed in a cell area;   detecting said first diffusion layer closest to a first boundary defining said cell area and said second diffusion layer closest to a second boundary defining said cell area in said cell in a first direction;   detecting a first distance between said first diffusion layer and said first boundary, and a second distance between said second diffusion layer and said second boundary in said first direction; and   producing a correction library data by correcting said library data so that said first distance and said second distance are set to have substantially a same value, when said first distance is different from said second distance.   
     
     
         11 . The layout program product as claimed in  claim 10 , wherein said correction library data is produced by changing a size of said cell area while keeping a size of said first and second diffusion layers. 
     
     
         12 . The layout program product as claimed in  claim 10 , wherein said cell comprises an inverter circuit. 
     
     
         13 . The layout program product as claimed in  claim 12 , wherein said cell comprises a NAND circuit. 
     
     
         14 . The layout program product as claimed in  claim 12 , comprising:
 reading said library data including said cell which further includes a gate extending in a second direction perpendicular to said first direction, said gate being arranged between said first and second diffusion layers;   detecting a first gate closest to said first boundary and a second gate closest to said second boundary in said cell in a first direction;   measuring a third distance between said first gate and said first boundary, and a fourth distance between said gate and said second boundary in said first direction; and   producing said correction library data by correcting said library data so that said first distance and said second distance are set to have substantially a same limit value, when said third distance is different from said fourth distance.   
     
     
         15 . The layout program product as claimed in  claim 14 , wherein said first gate is the same as said second gate. 
     
     
         16 . The layout program product as claimed in  claim 14 , wherein said first gate is different from said second gate. 
     
     
         17 . The layout program product as claimed in  claim 11 , further comprising:
 changing a number of terminals for said cell when said correction library data is produced.   
     
     
         18 . The layout program product as claimed in  claim 17 , further comprising:
 changing a location of terminals for said cell when said number of said terminals is changed.   
     
     
         19 . The layout program product as claimed in  claim 10 , wherein said cell of said library data is designable regardless of values of said first distance and said second distance, so that said first distance is different from said second distance when said cell is originally prepared in said library data. 
     
     
         20 . The layout program product as claimed in  claim 10 , further comprising:
 producing a chip layout data based on said correction library data and a net list.   
     
     
         21 . The semiconductor integrated circuit according to  claim 1 ,
 wherein a distance between adjacent diffusion layers of second cells adjacently arranged among said first and second cells, in said second direction, are substantially equal.