US2008308940A1PendingUtilityA1

Lateral current carrying capability improvement in semiconductor devices

Assignee: FEILCHENFELD NATALIE BARBARAPriority: Jul 27, 2006Filed: Aug 26, 2008Published: Dec 18, 2008
Est. expiryJul 27, 2026(~0 yrs left)· nominal 20-yr term from priority
H10W 20/4441H10W 20/4421H10W 20/47H10W 20/031H10D 84/401H10D 84/0109H10D 84/038
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Claims

Abstract

A semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

Claims

exact text as granted — not AI-modified
1 . A semiconductor structure, comprising:
 (a) a substrate;   (b) a semiconductor device on the substrate;   (c) N ILD (Inter-Level Dielectric) layers on the semiconductor device, wherein N is an integer greater than one; and   (d) an electrically conductive line in a top ILD layer of the N ILD layers,
 wherein the electrically conductive line is electrically coupled to the semiconductor device through a plurality of P vias and Q lines, 
 wherein P and Q are positive integers and P+Q is greater than 2, 
 wherein the plurality of P vias and Q lines overlap one another such that there exists an imaginary straight line that intersects all the plurality of P vias and Q lines, and 
 wherein the plurality of P vias and Q lines reside in the N ILD layers. 
   
   
   
       2 . The structure of  claim 1 ,
 wherein the electrically conductive line comprises copper, and   wherein the plurality of P vias and Q lines comprise copper.   
   
   
       3 . The structure of  claim 1 , further comprising a contact region, wherein the contact region electrically couples the electrically conductive line to the semiconductor device. 
   
   
       4 . The structure of  claim 3 , wherein the contact region comprises tungsten.

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