Integrated Processor Array, Instruction Sequencer And I/O Controller

Abstract

A computer processor having an integrated instruction sequencer, array of processing engines, and I/O controller. The instruction sequencer sequences instructions from a host, and transfers these instructions to the processing engines, thus directing their operation. The I/O controller controls the transfer of I/O data to and from the processing engines in parallel with the processing controlled by the instruction sequencer. The processing engines themselves are constructed with an integer arithmetic and logic unit (ALU), a 1-bit ALU, a decision unit, and registers. Instructions from the instruction sequencer direct the integer ALU to perform integer operations according to logic states stored in the 1-bit ALU and data stored in the decision unit. The 1-bit ALU and the decision unit can modify their stored information in the same clock cycle as the integer ALU carries out its operation. The processing engines also contain a local memory for storing instructions and data.

1 . A computer system, comprising:
 a processing array having processing engines serially interconnected in rows and columns so as to form rows of processing engines and columns of processing engines, the processing array configured to execute I/O operations by shifting I/O data sequentially through the columns of processing engines, to shift computation data sequentially across the rows of processing engines, and to execute computation operations upon the shifted computation data in parallel with the I/O operations;   an instruction sequencing unit configured to sequence instructions and to transfer the instructions to the processing engines of the processing array so as to control the computation operations; and   an I/O controller configured to exchange the I/O data with the processing engines of the processing array.   
   
   
       2 . The computer system of  claim 1 , wherein each of the processing engines further comprises:
 a logic unit configured to store a logic state and to modify the logic state according to the transferred instructions;   a decision unit configured to store a decision state and to modify the decision state according to the transferred instructions;   an integer unit configured to conditionally perform integer operations based on the decision state, the integer operations performed upon the shifted computation data according to the logic state and the transferred instructions;   registers in communication with the logic unit, the decision unit, and the integer unit, the registers configured to receive the shifted computation data and the logic state, and to transmit the shifted computation data and the logic state to the instruction sequencing unit; and   a local memory in communication with the registers and configured to store the shifted computation data.   
   
   
       3 . The computer system of  claim 2 , wherein:
 the decision state is a state selectively designating the processing engines as marked processing engines and unmarked processing engines;   the integer units are configured to perform the integer operations upon the designating as marked processing engines; and   the integer units are configured to suspend the integer operations upon the designating as unmarked processing engines.   
   
   
       4 . The computer system of  claim 2  wherein each of the integer units is further configured to perform:
 a first operation upon the shifted computation data according to one of the transferred instructions, when the logic state is a first logic state; and   a second operation upon the shifted computation data according to the one of the transferred instructions, when the logic state is a second logic state.   
   
   
       5 . The computer system of  claim 4  wherein the first operation and the second operation each are a shift operation shifting the stored data to another one of the processing engines, or an arithmetic operation. 
   
   
       6 . The computer system of  claim 5  further comprising an I/O interface in communication with the processing array and the I/O controller, the I/O interface configured to format the I/O data for storage in the local memories of the processing engines. 
   
   
       7 . The computer system of  claim 6  wherein the I/O interface is further configured to format the I/O data for loading in the local memories in shuffled mode. 
   
   
       8 . The computer system of  claim 6  wherein the I/O interface is further configured to format the I/O data by byte expanding the I/O data. 
   
   
       9 . The computer system of  claim 6  wherein the I/O interface is further configured to format the I/O data by word expanding the I/O data. 
   
   
       10 . The computer system of  claim 6  wherein the I/O interface is further configured to format the I/O data for loading in the local memories in direct transfer mode. 
   
   
       11 . The computer system of  claim 6  wherein the I/O interface is further configured to format the I/O data for loading in the local memories in indirect transfer mode. 
   
   
       12 . The computer system of  claim 1  further comprising a decoder unit in communication with the processing array and the instruction sequencing unit, the decoder unit having a decoder memory storing an instruction set having expanded instructions corresponding to the sequenced instructions received from the instruction sequencing unit, the decoder unit further configured to:
 receive the sequenced instructions from the instruction sequencing unit;   retrieve from the decoder memory those expanded instructions corresponding to the sequenced instructions received from the instruction sequencing unit; and   transmit the retrieved expanded instructions to the array of processing engines.   
   
   
       13 . The computer system of  claim 12  wherein the decoder memory is an SRAM memory. 
   
   
       14 . The computer system of  claim 12  wherein the sequenced instructions are 8-bit instructions, and the expanded instructions are 64-bit microcode instructions. 
   
   
       15 . The computer system of  claim 1  wherein:
 the instruction sequencing unit is further configured to instruct ones of the processing engines to generate addresses; and   the ones of the processing engines are further configured to generate addresses and to transmit the generated addresses to the I/O controller.