Method of fabricating non-volatile memory

Abstract

A method of fabricating a non-volatile memory is provided. A memory cell array having first memory units and second memory units is formed on a substrate. Then, a source region and a drain region are formed in the substrate on the respective sides of the memory cell array. Next, a patterned first inter-layer insulating layer is formed on the substrate to form a first trench and a number of second trenches. A conductive layer is formed on the substrate to form a source line in the first trench and conductive lines in the second trenches. A second inter-layer insulating layer is formed on the substrate and then a conductive plug having contact with the drain region is formed in the second inter-layer insulating layer and the first inter-layer insulating layer. Then, a bit line having contact with the conductive plug is formed on the second inter-layer insulating layer.

1 . A method of fabricating a non-volatile memory, comprising the steps of:
 providing a substrate;   forming a plurality of first memory units separated from one another by gaps on the substrate, wherein each first memory unit comprises a first composite layer, a first gate and a cap layer sequentially formed over the substrate;   forming a plurality of insulating spacers on the sidewalls of the first memory units;   forming a plurality of second memory units in the gaps between the first memory units, wherein each second memory unit comprises a second composite layer and a second gate sequentially formed on the substrate, and the second memory units together with the first memory units form a memory cell array;   forming a source region and a drain region in the substrate on the respective sides of the memory cell array;   forming a first inter-layer insulating layer on the substrate;   patterning the first inter-layer insulating layer to form a first trench and a plurality of second trenches, wherein the first trench exposes the source region and the second trenches expose the respective second gates of the second memory units in the same column;   forming a conductive layer over the substrate, wherein the conductive layer completely fills the first trench and the second trenches;   removing a portion of the conductive layer until the first inter-layer insulating layer is exposed so that a source line is formed in the first trench and a plurality of conductive lines is formed in the respective second trenches;   forming a second inter-layer insulating layer over the substrate;   forming a conductive plug in contact with the drain region in the second inter-layer insulating layer and the first inter-layer insulating layer; and   forming a bit line in contact with the conductive plug over the second inter-layer insulating layer.   
   
   
       2 . The method of  claim 1 , wherein the material constituting the first gate comprises polycide. 
   
   
       3 . The method of  claim 1 , wherein the material constituting the second gate comprises doped polysilicon. 
   
   
       4 . The method of  claim 1 , wherein the material constituting the source line and the conductive line comprises tungsten. 
   
   
       5 . The method of  claim 1 , wherein the step of removing a portion of the first conductive layer until the first inter-layer insulating layer is exposed comprises performing a chemical-mechanical polishing operation. 
   
   
       6 . The method of  claim 1 , wherein the first composite layer comprises a silicon oxide/silicon nitride/silicon oxide composite layer. 
   
   
       7 . The method of  claim 1 , wherein the second composite layer comprises a silicon oxide/silicon nitride/silicon oxide composite layer. 
   
   
       8 . A method of fabricating a non-volatile memory, comprising the steps of:
 providing a substrate;   forming a plurality of first memory units separated from one another by a gap on the substrate, wherein each first memory unit comprises a first composite layer, a first gate and a cap layer sequentially formed over the substrate;   forming a plurality of insulating spacers on the sidewalls of the first memory units;   forming a plurality of second memory units in the gaps between the first memory units, wherein each second memory unit comprises a second composite layer and a second gate sequentially formed on the substrate, and the second memory units together with the first memory units form a memory cell array;   forming a source region and a drain region in the substrate on the respective sides of the memory cell array;   forming a first inter-layer insulating layer on the substrate;   forming a source line that connects with the source region in the first inter-layer insulating layer;   forming a second inter-layer insulating layer over the first inter-layer insulating layer;   patterning the second inter-layer insulating layer and the first inter-layer insulating layer to form a plurality of first contact openings and a plurality of second contact openings, wherein the first contact openings expose the source line and the second contact openings expose the second gate of the second memory units;   forming a plurality of first conductive plugs inside the first contact openings and forming a plurality of second conductive plugs inside the second contact openings;   forming a first conductive line and a plurality of second conductive lines over the second inter-layer insulating layer, wherein the first conductive line connects with the first conductive plug and the second conductive lines connect with the second conductive plugs in the same column;   forming a third inter-layer insulating layer over the substrate;   forming a third conductive plug in contact with the drain region in the third inter-layer insulating layer, the second inter-layer insulating layer and the third inter-layer insulating layer; and   forming a bit line in contact with the third conductive plug over the third inter-layer insulating layer.   
   
   
       9 . The method of  claim 8 , wherein the material constituting the first conductive plug and the second conductive plugs comprises tungsten. 
   
   
       10 . The method of  claim 8 , wherein the material constituting the first conductive line and the second conductive lines comprises copper-aluminum alloy. 
   
   
       11 . The method of  claim 8 , wherein the first composite layer comprises a silicon oxide/silicon nitride/silicon oxide composite layer. 
   
   
       12 . The method of  claim 8 , wherein the second composite layer comprises a silicon oxide/silicon nitride/silicon oxide composite layer.