US2008303141A1PendingUtilityA1

Method for etching a substrate and a device formed using the method

Assignee: TEXAS INSTRUMENTS INCPriority: Nov 25, 2003Filed: Jun 12, 2008Published: Dec 11, 2008
Est. expiryNov 25, 2023(expired)· nominal 20-yr term from priority
H10W 20/0698H10P 50/283H10D 1/682
49
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Claims

Abstract

The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155 , in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130 . The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.

Claims

exact text as granted — not AI-modified
1 - 21 . (canceled) 
   
   
       22 . An integrated circuit, comprising:
 semiconductor devices located over a semiconductor substrate;   a dielectric layer located over said semiconductor devices, said dielectric layer having an aluminum oxide etch stop layer located thereunder; and   interconnects located in said dielectric layer and in contact with said aluminum oxide etch stop layer, said interconnects contacting said semiconductor devices thereby forming an operative integrated circuit.   
   
   
       23 . The integrated circuit as recited in  claim 22  wherein said dielectric layer and said aluminum oxide etch stop layer are located in a back-end of line of said integrated circuit. 
   
   
       24 . The integrated circuit as recited in  claim 22  wherein said dielectric layer is a first dielectric layer and said aluminum oxide etch stop layer is a first aluminum oxide etch stop layer, and further including multiple other dielectric layers and aluminum oxide etch stop layers located over said first dielectric layer and said first aluminum oxide etch stop layer. 
   
   
       25 . The integrated circuit as recited in  claim 24  being void of silicon nitride etch stop layers.

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