Semiconductor device with integrated trench lateral power MOSFETs and planar devices

Abstract

Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.

1 . A manufacturing method of a semiconductor device comprising at least one trench lateral power MOSFET on a semiconductor substrate, comprising a first gate oxide film and first gate electrodes that are positioned in a trench, a first drain region positioned under a bottom surface of the trench, first source regions positioned on both sides of the trench, an extended drain region positioned between the first drain region and the first source regions, a first drain electrode connected electrically to the first drain region, and first source electrodes connected electrically to the respective first source regions, and at least one planar MOSFET positioned on the semiconductor substrate, comprising a second gate oxide film and a second gate electrode that are positioned on a surface of the semiconductor substrate, a second drain region and a second source region that are positioned in a surface layer of the semiconductor substrate on both sides of the second gate electrode, a second drain electrode connected electrically to the second drain region, and a second source electrode connected electrically to the second source region, the manufacturing method comprising:
 forming the trench in the semiconductor substrate;   forming the extended drain region;   forming the first gate oxide film and the second gate oxide film;   forming first gate electrodes and the second gate electrode;   forming the first drain region, first source regions, the second drain region, and the second source region;   laying an interlayer insulating film over the surface of the semiconductor substrate;   etching the interlayer insulating film to expose the first drain region under the bottom surface of the trench;   filling the inside of the trench with a polysilicon layer that is in contact with the first drain region;   laying a passivation film over the surface of the semiconductor substrate;   etching the passivation film and the interlayer insulating film to expose the polysilicon layer, the first source regions, the second drain region, and the second source region; and   laying a metal layer on the passivation film and patterning the metal layer to form the first drain electrode, first source electrodes, the second drain electrode, and the second source electrode that are in contact with the polysilicon layer, the first source regions, the second drain region, and the second source region, respectively.   
     
     
         2 . The manufacturing method according to  claim 1 , wherein the polysilicon layer is laid over the surface of the semiconductor substrate after the first gate oxide film and the second gate oxide film have been formed, and then the polysilicon layer is patterned to form the first gate electrodes and the second gate electrode simultaneously. 
     
     
         3 . The manufacturing method according to  claim 1 , wherein the first gate oxide
 film and the second gate oxide film are formed simultaneously by forming an oxide film over the surface of the semiconductor substrate after the extended drain region has been formed.   
     
     
         4 . The manufacturing method according to  claim 1 , wherein a well region is
 formed in the semiconductor substrate, and then the trench is formed in the well region.   
     
     
         5 . The manufacturing method according to  claim 1 , wherein after the trench is
 formed in the semiconductor substrate, impurity diffusion is performed through the trench to form a well region that surrounds the trench.   
     
     
         6 . The manufacturing method according to  claim 1 , wherein selective oxidation
 films for device isolation are formed after the trench has been formed in the semiconductor substrate.   
     
     
         7 . The manufacturing method according to  claim 1 , wherein the trench is
 formed after selective oxidation films for device isolation have been formed on the semiconductor substrate.   
     
     
         8 . A semiconductor device comprising:
 a trench lateral power MOSFET on a semiconductor substrate, comprising   a first gate oxide film and first gate electrodes that are positioned in a trench;   a first source region of a second conductivity type positioned under a bottom surface of the trench;   first drain regions of a second conductivity type positioned on both sides of the trench;   an extended drain region of a second conductivity type and a base region of a first conductivity type to serve as channel regions, the extended drain region and the base region being positioned between the first source region and the first drain regions;   first drain electrodes connected electrically to the respective first drain regions; and   a first source electrode connected electrically to the first source region;   a first planar MOSFET positioned on the semiconductor substrate, comprising   a second gate oxide film and a second gate electrode that are positioned on a surface of the semiconductor substrate;   a second drain region of a first conductivity type and a second source region of a first conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the second gate electrode;   a second drain electrode connected electrically to the second drain region; and   a second source electrode connected electrically to the second source region; and   a second planar MOSFET positioned on the semiconductor substrate, comprising a third gate oxide film and a third gate electrode that are positioned on the surface of the semiconductor substrate;   a third drain region of a second conductivity type and a third source region of a second conductivity type that are positioned in the surface layer of the semiconductor substrate on both sides of the third gate electrode;   a third drain electrode connected electrically to the third drain region; and a third source electrode connected electrically to the third source region,   wherein the first drain electrodes, the first source electrode, the second drain electrode, the second source electrode, the third drain electrode, and the third source electrode are formed by patterning the same metal layer.   
     
     
         9 . The semiconductor device according to  claim 8 , wherein the first gate electrodes, the second gate electrode, and the third gate electrode are formed by patterning a polysilicon layer formed on the surface of the semiconductor substrate and inside the trench. 
     
     
         10 . The semiconductor device according to  claim 8 , further comprising a body region that is positioned under the bottom surface of the trench and has a same conductivity type as the base region. 
     
     
         11 . The semiconductor device according to  claim 8 , further comprising a barrier metal layer and a conductor that is one of an n-type or p-type semiconductor extending in the trench from the surface of the semiconductor substrate proximate to the bottom surface of the trench, wherein the first source electrode is in contact with the conductor, the conductor is in contact with the barrier metal layer, and the barrier metal layer is in contact with the first source region. 
     
     
         12 . The semiconductor device according to  claim 11 , further comprising a plug region that is positioned under the bottom surface of the trench and has a same conductivity type as the base region, wherein the barrier metal layer is in contact with the plug region. 
     
     
         13 . The semiconductor device according to  claim 10 , further comprising body regions that are positioned on both sides of the trench and have the same conductivity type as the base region. 
     
     
         14 . A semiconductor device comprising:
 a first trench lateral power MOSFET on a semiconductor substrate, comprising   a first gate oxide film and first gate electrodes that are positioned in a first trench;   a first source region of a second conductivity type positioned under a bottom surface of the first trench;   first drain regions of a second conductivity type positioned on both sides of the first trench;   a first extended drain region of a second conductivity type and a first base region of a first conductivity type to serve as channel regions, the first extended drain region and the first base region being positioned between the first source region and the first drain regions;   first drain electrodes connected electrically to the respective first drain regions; and   a first source electrode connected electrically to the first source region;   a second trench lateral power MOSFET positioned on the semiconductor substrate, comprising   a second gate oxide film and second gate electrodes that are positioned in a second trench;   a second source region of a first conductivity type positioned under a bottom surface of the second trench;   second drain regions of a first conductivity type positioned on both sides of the second trench;   a second extended drain region of a first conductivity type and a second base region of a second conductivity type to serve as channel regions, the second extended drain region and the second base region being positioned between the second source region and the second drain regions;   second drain electrodes connected electrically to the respective second drain regions; and   a second source electrode connected electrically to the second source region; and   a planar MOSFET positioned on the semiconductor substrate, comprising   a third gate oxide film and a third gate electrode that are positioned on a surface of the semiconductor substrate;   a third drain region of a second conductivity type and a third source region of a second conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the third gate electrode;   a third drain electrode connected electrically to the third drain region; and   a third source electrode connected electrically to the third source region,   wherein the first drain electrodes, the first source electrode, the second drain electrodes, the second source electrode, the third drain electrode, and the third source electrode are formed by patterning a same metal layer.   
     
     
         15 . The semiconductor device according to  claim 14 , wherein the first gate electrodes, the second gate electrodes, and the third gate electrode are formed by patterning a polysilicon layer formed on the surface of the semiconductor substrate and inside the trench. 
     
     
         16 . The semiconductor device according to  claim 14 , further comprising a first body region that is positioned under the bottom surface of the first trench and has a same conductivity type as the first base region. 
     
     
         17 . The semiconductor device according to  claim 16 , further comprising a second body region that is positioned under the bottom surface of the second trench and has a same conductivity type as the second base region. 
     
     
         18 . The semiconductor device according to  claim 14 , further comprising first and second barrier metal layers, a first conductor that is an n-type or p-type semiconductor extending in the first trench from the surface of the semiconductor substrate proximate to the bottom surface of the first trench, and a second conductor that is one of an n-type or p-type semiconductor extending in the second trench from the surface of the semiconductor substrate proximate to the bottom surface of the second trench, wherein the first source electrode is in contact with the first conductor, the first conductor is in contact with the first barrier metal layer, and the first barrier metal layer is in contact with the first source region, and wherein the second source electrode is in contact with the second conductor, the second conductor is in contact with the second barrier metal layer, and the second barrier metal layer is in contact with the second source region. 
     
     
         19 . The semiconductor device according to  claim 16 , further comprising body regions that are positioned on both sides of the first trench and have the same conductivity type as the first base region. 
     
     
         20 . The semiconductor device according to  claim 17 , further comprising body regions that are positioned on both sides of the second trench and have the same conductivity type as the second base region. 
     
     
         21 . A semiconductor device comprising:
 a first trench lateral power MOSFET on a semiconductor substrate, comprising   a first gate oxide film and first gate electrodes that are positioned in a first trench;   a first source region of a second conductivity type positioned under a bottom surface of the first trench;   first drain regions of a second conductivity type positioned on both sides of the first trench;   a first extended drain region of a second conductivity type and a first base region of a first conductivity type to serve as channel regions, the first extended drain region and the first base region being positioned between the first source region and the first drain regions;   first drain electrodes connected electrically to the respective first drain regions; and   a first source electrode connected electrically to the first source region;   a second trench lateral power MOSFET positioned on the semiconductor substrate, comprising   a second gate oxide film and second gate electrodes that are positioned in a second trench;   a second source region of a first conductivity type positioned under a bottom surface of the second trench;   second drain regions of a first conductivity type positioned on both sides of the second trench;   a second extended drain region of a first conductivity type and a second base region of a second conductivity type to serve as channel regions, the second extended drain region and the second base region being positioned between the second source region and the second drain regions;   second drain electrodes connected electrically to the respective second drain regions; and   a second source electrode connected electrically to the second source region;   a first planar MOSFET positioned on the semiconductor substrate, comprising   a third gate oxide film and a third gate electrode that are positioned on a surface of the semiconductor substrate;   a third drain region of a second conductivity type and a third source region of a second conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the third gate electrode;   a third drain electrode connected electrically to the third drain region; and   a third source electrode connected electrically to the third source region; and   a second planar MOSFET positioned on the semiconductor substrate, comprising   a fourth gate oxide film and a fourth gate electrode that are positioned on the surface of the semiconductor substrate;   a fourth drain region of a first conductivity type and a fourth source region of a first conductivity type that are positioned in the surface layer of the semiconductor substrate on both sides of the fourth gate electrode;   a fourth drain electrode connected electrically to the fourth drain region;   a fourth source electrode connected electrically to the fourth source region,   wherein the first drain electrodes, the first source electrode, the second drain electrodes, the second source electrode, the third drain electrode, the third source electrode, the fourth drain electrode, and the fourth source electrode are formed by patterning a same metal layer, and   wherein the first gate electrodes, the second gate electrodes, the third gate electrode, and the fourth gate electrode are formed by patterning a polysilicon layer formed on the surface of the semiconductor substrate and inside the trench.   
     
     
         22 . A semiconductor device comprising:
 a first trench lateral power MOSFET on a semiconductor substrate, comprising   a first gate oxide film and first gate electrodes that are positioned in a first trench;   a first source region of a second conductivity type positioned under a bottom surface of the first trench;   first drain regions of a second conductivity type positioned on both sides of the first trench;   a first extended drain region of a second conductivity type and a first base region of a first conductivity type to serve as channel regions, the first extended drain region and the first base region being positioned between the first source region and the first drain regions;   first drain electrodes connected electrically to the respective first drain regions; and   a first source electrode connected electrically to the first source region;   a second trench lateral power MOSFET positioned on the semiconductor substrate, comprising   a second gate oxide film and second gate electrodes that are positioned in a second trench;   a second source region of a first conductivity type positioned under a bottom surface of the second trench;   second drain regions of a first conductivity type positioned on both sides of the second trench;   a second extended drain region of a first conductivity type and a second base region of a second conductivity type to serve as channel regions, the second extended drain region and the second base region being positioned between the second source region and the second drain regions;   second drain electrodes connected electrically to the respective second drain regions; and   a second source electrode connected electrically to the second source region;   a first planar MOSFET positioned on the semiconductor substrate, comprising   a third gate oxide film and a third gate electrode that are positioned on a surface of the semiconductor substrate;   a third drain region of a second conductivity type and a third source region of a second conductivity type that are positioned in a surface layer of the semiconductor substrate on both sides of the third gate electrode;   a third drain electrode connected electrically to the third drain region; and   a third source electrode connected electrically to the third source region; and   a second planar MOSFET positioned on the semiconductor substrate, comprising   a fourth gate oxide film and a fourth gate electrode that are positioned on the surface of the semiconductor substrate;   a fourth drain region of a first conductivity type and a fourth source region of a first conductivity type that are positioned in the surface layer of the semiconductor substrate on both sides of the fourth gate electrode;   a fourth drain electrode connected electrically to the fourth drain region;   a fourth source electrode connected electrically to the fourth source region; and   a first body region that is positioned under the bottom surface of the first trench and has a same conductivity type as the first base region,   wherein the first drain electrodes, the first source electrode, the second drain electrodes, the second source electrode, the third drain electrode, the third source electrode, the fourth drain electrode, and the fourth source electrode are formed by patterning a same metal layer.   
     
     
         23 . The semiconductor device according to  claim 22 , further comprising a second body region that is positioned under the bottom surface of the second trench and has a same conductivity type as the second base region.