One-time programmable read-only memory

Abstract

A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a gate dielectric layer, a first gate and a second gate. The substrate is of a first conductive type. The first doped region and the second doped region are of a second conductive type and are separately disposed in the substrate. The gate dielectric layer is disposed on the substrate between the first doped region and the second doped region. The first gate and the second gate are disposed on the gate dielectric layer, respectively. The first gate is adjacent to the first doped region, while the second gate is adjacent to the second doped region. Here, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect.

1 . A one-time programmable read-only memory (OTP-ROM), comprising:
 a substrate which is of a first conductive type;   a first doped region and a second doped region which are of a second conductive type and are separately disposed in the substrate;   a gate dielectric layer disposed on the substrate between the first doped region and the second doped region; and   a first gate and a second gate respectively disposed on the gate dielectric layer, the first gate being adjacent to the first doped region, the second gate being adjacent to the second doped region, wherein   the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect.   
   
   
       2 . The OTP-ROM according to  claim 1 , wherein the first gate is shorter than the second gate to lower programming voltage, and the second gate is long enough not to be breakdown after programming operation. 
   
   
       3 . The OTP-ROM according to  claim 1 , wherein the gate dielectric layer is uniformly formed. 
   
   
       4 . The OTP-ROM according to  claim 1 , wherein the gate dielectric layer has a first thickness and a second thickness, the gate dielectric layer having the first thickness is disposed below the first gate, the gate dielectric layer having the second thickness is disposed below the second gate, and the first thickness is less than the second thickness. 
   
   
       5 . The OTP-ROM according to  claim 1 , wherein the gate dielectric layer disposed below the first gate has a third thickness and a fourth thickness, the gate dielectric layer having the third thickness is adjacent to the first doped region, the gate dielectric layer having the fourth thickness is adjacent to the second doped region, and the third thickness is different from the fourth thickness. 
   
   
       6 . The OTP-ROM according to  claim 5 , wherein the third thickness is greater than the fourth thickness. 
   
   
       7 . The OTP-ROM according to  claim 5 , wherein the third thickness is less than the fourth thickness. 
   
   
       8 . The OTP-ROM according to  claim 1 , wherein the first gate is coupled to the first doped region. 
   
   
       9 . The OTP-ROM according to  claim 8 , wherein the method of programming the OTP-ROM is under the conditions that:
 a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.   
   
   
       10 . The OTP-ROM according to  claim 8 , wherein the method of programming the OTP-ROM is under the conditions that:
 a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region and a triggering current to be sunk by the first doped region, and the substrate is at a reference voltage.   
   
   
       11 . The OTP-ROM according to  claim 8 , wherein the method of reading the OTP-ROM is under the conditions that:
 a voltage of the second doped region is set at a reading voltage, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.   
   
   
       12 . The OTP-ROM according to  claim 1 , wherein the first gate is coupled to the second doped region. 
   
   
       13 . The OTP-ROM according to  claim 12 , wherein the method of programming the OTP-ROM is under the conditions that:
 a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.   
   
   
       14 . The OTP-ROM according to  claim 12 , wherein the method of programming the OTP-ROM is under the conditions that:
 a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region and a triggering current to be sunk by the first doped region, and the substrate is at a reference voltage.   
   
   
       15 . The OTP-ROM according to  claim 1 , further comprising a third doped region which is of the second conductive type, the third doped region being disposed in the substrate between the first gate and the second gate, but not aligned with the first gate and second gate, wherein the first gate is coupled to the third doped region. 
   
   
       16 . The OTP-ROM according to  claim 15 , wherein the method of programming the OTP-ROM is under the conditions that:
 a voltage of the first doped region is higher than a voltage of the second doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the second doped region and the substrate are at a reference voltage.   
   
   
       17 . The OTP-ROM according to  claim 15 , wherein the method of programming the OTP-ROM is under the conditions that:
 a voltage of the first doped region is higher than a voltage of the second doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region and a triggering current to be sunk by the second doped region, and the substrate is at a reference voltage.   
   
   
       18 . The OTP-ROM according to  claim 1 , wherein the method of reading the OTP-ROM is under the conditions that:
 a voltage of the second doped region is set at a reading voltage, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.   
   
   
       19 . The OTP-ROM according to  claim 1 , wherein the method of reading the OTP-ROM is under the conditions that:
 a voltage of the first doped region is set at a reading voltage, the voltage of the second gate is higher than a threshold voltage to pass the voltage to second doped region, and the second doped region and the substrate are at a reference voltage.