Discrete Trap Memory (DTM) Mediated by Fullerenes

Abstract

A discrete trap memory, comprising a silicon substrate layer, a bottom oxide layer on the silicon substrate layer, a Fullerene layer on the bottom oxide layer, a top oxide layer on the Fullerene layer, and a gate layer on the top oxide layer; wherein the Fullerene layer comprises spherical, elliptical or endohedral Fullerenes that act as charge traps.

1 . An integrated circuit device, comprising:
 a Fullerene layer having a plurality of Fullerene molecules, wherein the Fullerene molecules act as charge traps.   
     
     
         2 . The integrated circuit device of  claim 1 , wherein the plurality of Fullerenes are spherical or elliptical Fullerenes. 
     
     
         3 . The integrated circuit device of  claim 1 , wherein the plurality of Fullerenes are endohedral Fullerenes. 
     
     
         4 . The integrated circuit device of  claim 1 , wherein the plurality of Fullerenes are arranged to form a single layer of Fullerenes. 
     
     
         5 . The integrated circuit device of  claim 1 , wherein the Fullerenes are Hetrofullerenes. 
     
     
         6 . A discrete trap memory, comprising:
 a silicon substrate layer;   a bottom dielectric layer on the silicon substrate layer;   a Fullerene layer on the bottom dielectric layer;   a top dielectric layer on the Fullerene layer; and   a gate layer on the top dielectric layer.   
     
     
         7 . The discrete trap memory of  claim 6 , wherein the Fullerene layer further comprises:
 a plurality of Fullerenes arranged in a single layer.   
     
     
         8 . The discrete trap memory of  claim 6 , wherein the Fullerene layer comprises Hetrofullerenes. 
     
     
         9 . The discrete trap memory of  claim 6 , wherein the Fullerene layer further comprises:
 a plurality of endohedral Fullerenes that act as charge traps.   
     
     
         10 . The discrete trap memory of  claim 6 , wherein the Fullerene layer further comprises:
 a plurality of spherical or elliptical Fullerenes that act as charge traps.   
     
     
         11 . The discrete trap memory of  claim 6 , wherein a material forming the bottom dielectric layer is selected from the group consisting of:
 a high-k dielectric;   an insulator;   a tunnel barrier;   an oxide;   silicon oxide;   Al 2 O 3 ;   HfO 2 ;   SiC; and   SiN.   
     
     
         12 . The discrete trap memory of  claim 6 , wherein a material forming the top dielectric layer is selected from the group consisting of:
 a high-k dielectric;   an insulator;   a tunnel barrier;   an oxide;   silicon oxide;   Al 2 O 3 ;   HfO 2 ;   SiC; and   SiN.   
     
     
         13 . A method for manufacturing a discrete trap memory device, comprising:
 arranging a plurality of Fullerenes on an oxide layer to form a mask, wherein the oxide layer is exposed through the mask at gaps between the plurality of Fullerenes;   depositing nano-crystals over the mask; and   trapping the nano-crystals in gaps between the plurality of Fullerenes.   
     
     
         14 . The method of  claim 13 , further comprising:
 removing the plurality of Fullerenes, wherein nano-crystals remaining on the oxide layer act as charge traps in the discrete memory device.   
     
     
         15 . The method of  claim 14 , further comprising:
 thermally growing the oxide layer on a silicon substrate;   depositing silicon oxide over the nano-crystals; and   forming a gate layer over the silicon oxide.   
     
     
         16 . A method for manufacturing a discrete trap memory device, comprising:
 arranging a plurality of Fullerenes on a bottom dielectric layer to form a mask, wherein the bottom dielectric layer is exposed through the mask at gaps between the plurality of Fullerenes;   depositing nano-crystals over the mask; and   trapping the nano-crystals in gaps between the plurality of Fullerenes.   
     
     
         17 . The method of  claim 16 , further comprising:
 removing the plurality of Fullerenes, wherein nano-crystals remaining on the bottom dielectric layer act as charge traps in the discrete memory device.   
     
     
         18 . The method of  claim 17 , further comprising:
 thermally growing the bottom dielectric layer on a silicon substrate;   depositing a top dielectric layer over the nano-crystals; and   forming a gate layer over the top dielectric layer.   
     
     
         19 . The method of  claim 16 , wherein a material forming the bottom dielectric layer is selected from the group consisting of:
 a high-k dielectric;   an insulator;   a tunnel barrier;   an oxide;   silicon oxide;   Al 2 O 3 ;   HfO 2 ;   SiC; and   SiN.   
     
     
         20 . The method of  claim 16 , wherein a material forming the top dielectric layer is selected from the group consisting of:
 a high-k dielectric;   an insulator;   a tunnel barrier;   an oxide;   silicon oxide;   Al 2 O 3 ;   HfO 2 ;   SiC; and   SiN.