Method of fabricating polycrystalline silicon layer, tft fabricated using the same, method of fabricating tft, and organic light emitting diode display device having the same

Abstract

A method of fabricating a polycrystalline silicon layer includes: forming an amorphous silicon layer on a substrate; crystallizing the amorphous silicon layer into a polycrystalline silicon layer using a crystallization-inducing metal; forming a metal layer pattern or metal silicide layer pattern in contact with an upper or lower region of the polycrystalline silicon layer corresponding to a region excluding a channel region in the polycrystalline silicon layer; and annealing the substrate to getter the crystallization-inducing metal existing in the channel region of the polycrystalline silicon layer to the region in the polycrystalline silicon layer having the metal layer pattern or metal silicide layer pattern. Accordingly, the crystallization-inducing metal existing in the channel region of the polycrystalline silicon layer can be effectively removed, and thus a thin film transistor having an improved leakage current characteristic and an OLED display device including the same can be fabricated.

1 . A method of removing a crystallization-inducing metal from a first predetermined region of a polycrystalline silicon layer crystallized using a crystallization-inducing metal, the method comprising:
 providing a metal layer pattern or metal silicide layer pattern in contact with the polycrystalline silicon layer in a second predetermined region of the polycrystalline silicon layer; and   performing annealing to getter the crystallization-inducing metal existing in the first predetermined region to the second predetermined region.   
     
     
         2 . The method of  claim 1 , wherein the providing of the metal layer pattern or metal silicide layer pattern in contact with the polycrystalline silicon layer in a second predetermined region of the polycrystalline silicon layer is carried out by forming the metal layer pattern or metal silicide layer pattern on the polycrystalline silicon layer in the second predetermined region of the polycrystalline silicon layer. 
     
     
         3 . The method of  claim 1 , wherein the providing of the metal layer pattern or metal silicide layer pattern in contact with the polycrystalline silicon layer in a second predetermined region of the polycrystalline silicon layer is carried out by forming the metal layer pattern or metal silicide layer pattern on a substrate, forming an amorphous silicon layer such that a first region of the amorphous silicon layer that becomes the first predetermined region contacts the substrate and a second region of the amorphous silicon layer that becomes the second predetermined region contacts the metal layer pattern or metal silicide layer pattern and crystallizing the amorphous silicon layer using a crystallization-inducing metal to form the polycrystalline silicon layer. 
     
     
         4 . The method of  claim 1 , wherein the second predetermined region is formed at a distance of 50 μm or less from the first predetermined region. 
     
     
         5 . The method according to  claim 1 , wherein the metal or metal silicide included in the metal layer pattern or metal silicide layer pattern has a smaller diffusion coefficient than the diffusion coefficient of the crystallization-inducing metal in the polycrystalline silicon layer. 
     
     
         6 . The method according to  claim 5 , wherein the metal or metal silicide included in the metal layer pattern or metal silicide layer pattern has a diffusion coefficient of 1/100 or less of the diffusion coefficient of the crystallization-inducing metal. 
     
     
         7 . The method according to  claim 6 , wherein the crystallization-inducing metal comprises nickel, and the diffusion coefficient of the metal or metal silicide included in the metal layer pattern or metal silicide layer pattern is from more than 0 to 10 −7  cm 2 /s. 
     
     
         8 . The method according to  claim 6 , wherein the metal layer pattern or metal silicide layer pattern comprises one selected from the group consisting of scandium (Sc), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), manganese (Mn), rhenium (Re), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), platinum (Pt), yttrium (Y), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), dysprosium (Dy), holmium (Ho), titanium nitride (TiN), tantalum nitride (TaN) and an alloy or silicide thereof. 
     
     
         9 . The method according to  claim 1 , wherein the annealing is performed for 10 seconds to 10 hours at a temperature of 500 to 993° C. 
     
     
         10 . The method of  claim 1 , wherein the metal layer pattern or metal silicide layer pattern when formed does not include any metal or metal silicide having a diffusion coefficient greater than 10 −7  cm 2 /s. 
     
     
         11 . The method according to  claim 1 , wherein the polycrystalline silicon layer crystallized using a crystallization-inducing metal is formed by a metal-induced crystallization (MIC) technique, a metal-induced lateral crystallization (MILC) technique or a super grain silicon (SGS) technique. 
     
     
         12 . The method according to  claim 1 , wherein the metal layer pattern or metal silicide layer pattern is formed to a thickness of 30 to 10000 Å. 
     
     
         13 . The method according to  claim 12 , wherein the metal layer pattern or metal silicide layer pattern is formed to a thickness of 30 to 2000 Å. 
     
     
         14 . The method according to  claim 1 , further comprising:
 implanting an n-type impurity or a p-type impurity into the region of the polycrystalline silicon layer corresponding to the metal layer pattern or metal silicide layer pattern, or forming a damage region in the region of the semiconductor layer corresponding to the metal layer pattern or metal silicide layer pattern using ions or plasma.   
     
     
         15 . The method according to  claim 1 , wherein the first predetermined region is a channel region in the polycrystalline silicon layer. 
     
     
         16 . A thin film transistor, comprising:
 a substrate;   a semiconductor layer disposed on the substrate and including a channel region, and source and drain regions;   a metal layer pattern or metal silicide layer pattern disposed over or under the semiconductor layer corresponding to a region excluding the channel region;   a gate electrode disposed to correspond to the channel region of the semiconductor layer;   a gate insulating layer interposed between the gate electrode and the semiconductor layer to insulate the semiconductor layer from the gate electrode; and   source and drain electrodes electrically connected to the source and drain regions of the semiconductor layer.   
     
     
         17 . The thin film transistor according to  claim 16 , wherein the metal layer pattern or metal silicide layer pattern includes a metal or metal silicide having a smaller diffusion coefficient in the semiconductor layer than the crystallization-inducing metal or an alloy thereof. 
     
     
         18 . The thin film transistor according to  claim 17 , wherein the metal or metal silicide included in the metal layer pattern or metal silicide layer pattern has a diffusion coefficient of 1/100 or less of that of the crystallization-inducing. 
     
     
         19 . The thin film transistor according to  claim 18 , wherein the crystallization-inducing metal comprises nickel, and the diffusion coefficient of the metal or metal silicide included in the metal layer pattern or metal silicide layer pattern is from more than 0 to 10 −7  cm 2 /s. 
     
     
         20 . The thin film transistor according to  claim 17 , wherein the metal layer pattern or metal silicide layer pattern comprises one selected from the group consisting of Sc, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Mn, Re, Ru, Os, Co, Rh, Ir, Pt, Y, La, Ce, Pr, Nd, Dy, Ho, TiN, TaN and an alloy or silicide thereof. 
     
     
         21 . The thin film transistor according to  claim 16 , wherein the metal layer pattern or metal silicide layer pattern is spaced 50 μm or less apart from the channel region of the semiconductor layer. 
     
     
         22 . The thin film transistor according to  claim 16 , wherein the metal layer pattern or metal silicide layer pattern has a thickness of 30 to 10000 Å. 
     
     
         23 . The thin film transistor according to  claim 16 , further comprising:
 an n-type impurity or a p-type impurity in a predetermined region of the semiconductor layer corresponding to the metal layer pattern or metal silicide layer pattern, or a damage region formed in the predetermined region of the semiconductor layer corresponding to the metal layer pattern or metal silicide layer pattern using ions or plasma.   
     
     
         24 . The thin film transistor according to  claim 16 , wherein a concentration of a crystallization-inducing metal in the channel region of the semiconductor layer is less than 10 13  atmos/cm 2 . 
     
     
         25 . A method of fabricating a thin film transistor, comprising:
 preparing a substrate;   forming an amorphous silicon layer on the substrate;   crystallizing the amorphous silicon layer into a polycrystalline silicon layer using crystallization-inducing metal;   forming a metal layer pattern or metal silicide layer pattern in contact with an upper or lower region of the polycrystalline silicon layer corresponding to a region excluding a channel region in the polycrystalline silicon layer;   forming a gate electrode corresponding to the channel region of the polycrystalline silicon layer;   forming a gate insulating layer between the gate electrode and the polycrystalline silicon layer to insulate the polycrystalline silicon layer from the gate electrode;   forming source and drain electrodes electrically connected to source and drain regions of the polycrystalline silicon layer; and   after forming the metal layer pattern or metal silicide layer pattern, annealing the substrate to getter the crystallization-inducing metal existing in the channel region of the polycrystalline silicon layer to a region of the polycrystalline silicon layer corresponding to the metal layer pattern or metal silicide layer pattern.   
     
     
         26 . The method according to  claim 25 , further comprising:
 after annealing the substrate to getter the crystallization-inducing metal existing in the channel region of the polycrystalline silicon layer, removing the metal layer pattern or metal silicide layer pattern.   
     
     
         27 . The method according to  claim 25 , wherein the metal layer pattern or metal silicide layer pattern includes a metal or metal silicide having a smaller diffusion coefficient in the polycrystalline silicon layer than that of the crystallization-inducing metal or an alloy thereof. 
     
     
         28 . The method according to  claim 27 , wherein the metal or metal silicide of the metal layer pattern or metal silicide layer pattern has a diffusion coefficient of 1/100 or less of that of the crystallization-inducing metal. 
     
     
         29 . The method according to  claim 28 , wherein the crystallization-inducing metal comprises nickel, and the diffusion coefficient of the metal or metal silicide of the metal layer pattern or metal silicide layer pattern is more than 0 to 10 −7  cm 2 /s or less. 
     
     
         30 . The method according to  claim 28 , wherein the metal layer pattern or metal silicide layer pattern comprises one selected from the group consisting of Sc, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Mn, Re, Ru, Os, Co, Rh, Ir, Pt, Y, La, Ce, Pr, Nd, Dy, Ho, TiN, TaN and an alloy or silicide thereof. 
     
     
         31 . The method according to  claim 25 , wherein the annealing is performed for 10 seconds to 10 hours at a temperature of 500 to 993° C. 
     
     
         32 . The method according to  claim 25 , wherein the crystallizing of the amorphous silicon layer is performed by an MIC, MILC or SGS technique. 
     
     
         33 . The method according to  claim 25 , further comprising:
 implanting an n-type impurity or a p-type impurity into the region of the polycrystalline silicon layer corresponding to the metal layer pattern or metal silicide layer pattern, or forming a damage region in the region of the polycrystalline silicon layer corresponding to the metal layer pattern or metal silicide layer pattern using ions or plasma.   
     
     
         34 . An organic light emitting diode (OLED) display device, comprising:
 a substrate;   a semiconductor layer disposed on the substrate, and including a channel region and source and drain regions;   a metal layer pattern or metal silicide layer pattern disposed over or under the semiconductor layer corresponding to a region excluding the channel region;   a gate electrode disposed to correspond to the channel region of the semiconductor layer;   a gate insulating layer interposed between the gate electrode and the semiconductor layer to insulate the semiconductor layer from the gate electrode;   source and drain electrodes electrically connected to the source and drain regions of the semiconductor layer;   a first electrode electrically connected to one of the source and drain electrodes;   an organic layer disposed on the first electrode; and   a second electrode disposed on the organic layer.   
     
     
         35 . The OLED display device according to  claim 34 , wherein the metal layer pattern or metal silicide layer pattern includes a metal or metal silicide having a smaller diffusion coefficient in the semiconductor layer than the crystallization-inducing metal or an alloy thereof. 
     
     
         36 . The OLED display device according to  claim 34 , wherein the metal or metal silicide of the metal layer pattern or metal silicide layer pattern has a diffusion coefficient of 1/100 or less of that of the crystallization-inducing metal. 
     
     
         37 . The OLED display device according to  claim 36 , wherein the crystallization-inducing metal comprises nickel, and the diffusion coefficient of the metal layer pattern or metal silicide layer pattern is from more than 0 to 10 −7  cm 2 /s. 
     
     
         38 . The OLED display device according to  claim 36 , wherein the metal layer pattern or metal silicide layer pattern comprises one selected from the group consisting of Sc, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Mn, Re, Ru, Os, Co, Rh, Ir, Pt, Y, La, Ce, Pr, Nd, Dy, Ho, TiN, TaN and an alloy thereof, or silicide thereof. 
     
     
         39 . The OLED display device according to  claim 34 , wherein the metal layer pattern or metal silicide layer pattern is spaced 50 μm or less apart from the channel region of the semiconductor layer. 
     
     
         40 . The OLED display device according to  claim 34 , wherein the metal layer pattern or metal silicide layer pattern has a thickness of 30 to 10000 Å. 
     
     
         41 . The OLED display device according to  claim 34 , further comprising:
 an n-type impurity or a p-type impurity in the semiconductor layer corresponding to the metal layer pattern or metal silicide layer pattern, or a damage region formed in the semiconductor layer corresponding to the metal layer pattern or metal silicide layer pattern using ions or plasma.   
     
     
         42 . The OLED display device according to  claim 34 , wherein the channel region of the semiconductor layer is devoid of a crystallization-inducing metal.