Method to Detect a Stalled Instruction Stream and Serialize Micro-Operation Execution

Abstract

A computer implemented method, apparatus, and computer usable program code for ensuring forward progress of instructions in a pipeline of a processor. Instructions are received in the pipeline. Instruction flushes are counted in the pipeline to determine a flush count. A single step mode in the pipeline is entered in response to the flush count exceeding a threshold. The single step mode instructions are issued in serial such that an instruction is not issued for execution until a prior instruction has completed execution.

1 - 12 . (canceled) 
   
   
       13 . A processor comprising:
 a completion unit for completing instructions in a pipeline of the processor, wherein the pipeline receives an architected instruction that is implemented using microcode that includes a plurality of micro-instructions, the completion unit further comprising:   a detection subsystem, wherein the detection subsystem includes a component that includes a counter for counting a number of flush instructions in the pipeline using the counter to determine a flush count, wherein the component receives a completion signal in response to the architected instruction completing successfully, wherein the component receives the flush instruction in response to flushing one of the plurality of micro-instructions, wherein the component outputs control signals that are used to control the counter, wherein the control signals is selected using the completion signal and the flush instruction; wherein the detection subsystem forces the pipeline of the processor to enter a single step mode if the flush count exceeds a threshold, wherein in single step mode the plurality of micro-instructions are executed in serial in the pipeline such that a next micro-instruction is not issued for execution in the pipeline until a prior micro-instruction has executed, and further wherein the single step mode is exited and the pipeline is returned to fully pipelined mode responsive to the architected instruction completing.   
   
   
       14 . The system of  claim 13 , wherein the completion unit monitors the architected instruction in the pipeline to the processor to determine if the architected instruction is stalled and asserts the flush instruction in response to the architected instruction stalling. 
   
   
       15 . The system of  claim 13 , wherein the detection subsystem resets the counter to zero in response to the architected instruction being completed, wherein a completion of the architected instruction indicates forward progress, wherein the processor exits the single step mode in the pipeline and returns to a fully pipelined mode in response to the counter being reset to zero. 
   
   
       16 . The system of  claim 15 , wherein the detection subsystem forces the pipeline of the processor to enter a single step mode when the detection subsystem receives any of a synchronization instruction, a debug mode control signal, and a slow mode control signal. 
   
   
       17 - 20 . (canceled)