Transistor design self-aligned to contact

Abstract

The present invention provides a method of manufacturing a transistor device, a transistor device, and a method for manufacturing an integrated circuit. In one aspect, the method of manufacturing a transistor device includes providing a gate structure ( 140 ) over a substrate ( 110 ). An insulating layer ( 310 ) is formed over the gate structure ( 140 ), and openings ( 710 ) to the substrate ( 110 ) are formed therein, thereby removing a portion of the gate structure ( 140 ). The openings ( 710 ) are filled with a conductor ( 1410 ), thereby forming an interconnect ( 1510 ).

1 . A transistor device, comprising:
 a gate structure comprising a gate electrode and a gate dielectric, said gate dielectric located between said gate electrode and a substrate;   a spacer layer substantially conforming to a sidewall of said gate structure; and   an interconnect extending through an insulating layer located over said gate structure and contacting said substrate, wherein said interconnect is in direct contact with said spacer layer.   
     
     
         2 . The transistor device as recited in  claim 1  wherein the gate structure has an I-beam shape. 
     
     
         3 . The transistor device as recited in  claim 1  wherein the spacer layer includes two or more layers. 
     
     
         4 . The transistor device as recited in  claim 1  wherein the interconnect includes a first segment parallel to a long axis of said gate structure and a second segment anti-parallel to said long axis. 
     
     
         5 . The transistor device as recited in  claim 4  wherein the second segment is normal to said long axis. 
     
     
         6 . The transistor device as recited in  claim 4  wherein the first segment includes a first narrow portion and a second wider portion.