Semiconductor device having n-channel type MOS transistor with gate electrode layer featuring small average polycrystalline silicon grain size

Abstract

In a semiconductor device including a semiconductor substrate, and an n-channel type MOS transistor produced in the semiconductor substrate, the n-channel type MOS transistor includes a gate insulating layer formed on the semiconductor substrate and having a thickness of at most 1.6 nm, and a gate electrode layer on the gate insulating layer, and the gate electrode layer is composed of polycrystalline silicon which has an average grain size falling within a range between 10 nm and 150 nm in the vicinity of the gate insulating layer.

1 . A semiconductor device comprising:
 a semiconductor substrate; and   a metal oxide semiconductor (MOS) transistor produced in said semiconductor substrate,   wherein said MOS transistor includes a gate insulating layer formed on said semiconductor substrate and having a thickness of at most 1.6 nm, and a gate electrode layer on said gate insulating layer, and   wherein said gate electrode layer is composed of polycrystalline silicon which has an average grain size falling within a range between 10 nm and 150 nm in the vicinity of said gate insulating layer.   
   
   
       2 . The semiconductor device as set forth in  claim 1 , wherein said MOS transistor comprises an n-channel type MOS transistor. 
   
   
       3 . The semiconductor device as set forth in  claim 2 , further comprising a p-channel type MOS transistor produced in said semiconductor substrate, wherein said p-channel type MOS transistor includes a gate insulating layer formed on said semiconductor substrate and having the same thickness as that of the gate insulating layer of said n-channel type MOS transistor, and a gate electrode layer on the gate insulating layer of said p-channel type MOS transistor and composed of polycrystalline silicon having an average grain size larger than that of the polycrystalline silicon of the gate electrode layer of said n-channel type MOS transistor. 
   
   
       4 . The semiconductor device as set forth in  claim 1 , wherein the gate electrode layer of said MOS transistor contains inert gas implanted thereinto at a given density. 
   
   
       5 . The semiconductor device as set forth in  claim 4 , wherein the given density of said inert gas falls within a range between 2×10 21  cm −3  and 1×10 22  cm −3 . 
   
   
       6 . The semiconductor device as set forth in  claim 4 , wherein said inert gas comprises nitrogen gas. 
   
   
       7 . The semiconductor device as set forth in  claim 3 , wherein the gate electrode layer of said n-channel type MOS transistor contains inert gas implanted thereinto at a given density, and wherein both the gate electrode layer of said n-channel type MOS transistor and the gate electrode layer of said p-channel type MOS transistor are integrated with each other to thereby establish an electrical connection therebetween. 
   
   
       8 . The semiconductor device as set forth in  claim 1 , wherein the gate electrode layer of said MOS transistor includes a first polycrystalline silicon layer formed on said semiconductor substrate, a stopper layer formed on said first polycrystalline silicon layer, and a second polycrystalline layer formed on said stopper layer, said first polycrystalline silicon layer featuring said average grain size falling within said range between 10 nm and 150 nm. 
   
   
       9 . The semiconductor device as set forth in  claim 8 , wherein said stopper layer has a thickness falling within a range between 0.5 nm and 2 nm. 
   
   
       10 . The semiconductor device as set forth in  claim 8 , wherein said stopper layer is formed as an insulating layer composed of one selected from the group consisting of silicon dioxide, silicon nitride and silicon carbide. 
   
   
       11 . The semiconductor device as set forth in  claim 8 , wherein said first polycrystalline silicon layer has a thickness falling within a range between 10 nm and 50 nm.