Semiconductor integrated circuit capable of testing with small scale circuit configuration

Abstract

In a test mode, a comparator compares for each column a value of data read from each memory cell connected to an activated word line with an expected value to be read from each memory cell. An error register holds error data based on a comparison result by a comparator. Each bit of the error data indicates the comparison result by the comparator for a corresponding column. Each bit is set to “0” when the comparison result for the corresponding column always indicates equality whichever word line is activated, and is set to “1” when once the comparison result for the corresponding column indicates difference.

1 . A semiconductor integrated circuit comprising:
 a comparator comparing a value of data read from each memory cell connected to an activated word line with an expected value to be read from said each memory cell, for each column in a test mode; and   an error register accumulatively holding error data based on a comparison result by said comparator, wherein   each bit of said error data indicates said comparison result by said comparator for a corresponding column,   said each bit takes a first logical value when said comparison result for said corresponding column always indicates equality whichever word line is activated, and takes a second logical value when once said comparison result for said corresponding column indicates difference,   said semiconductor integrated circuit has a plurality of modules having their operations controlled by respective chip select signals,   said each module has a control circuit controlling an operation of reading or writing data from or into a memory cell, irrespective of a value of said chip select signal, in the test mode,   said plurality of modules receive a common address signal sent through a common internal address bus, and   where said plurality of modules have word lines different in number, said control circuit in a module that does not have a maximum number of word lines controls an operation of reading or writing data from or to a memory cell, irrespective of a value of said chip select signal, only when values of one or more prescribed bits forming an address signal are prescribed values, and said prescribed bits are used in specifying a word line of a module having a maximum number of word lines and are not used in specifying a word line of said module that does not have a maximum number of word lines.   
   
   
       2 . A semiconductor integrated circuit comprising:
 a comparator comparing a value of data read from each memory cell connected to an activated word line with an expected value to be read from said each memory cell, for each column in a test mode; and   an error register accumulatively holding error data based on a comparison result by said comparator, wherein   each bit of said error data indicates said comparison result by said comparator for a corresponding column,   said each bit takes a first logical value when said comparison result for said corresponding column always indicates equality whichever word line is activated, and takes a second logical value when once said comparison result for said corresponding column indicates difference,   said semiconductor integrated circuit has a plurality of banks receiving a common address signal and having their operations controlled by one or more bits forming said address signal, and   said each bank includes a control circuit controlling an operation of reading or writing data from or into a memory cell, irrespective of values of said one or more bits forming an address signal controlling said operation.