Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device includes a memory cell which includes a first gate insulation film provided on the semiconductor substrate; a floating gate electrode provided on the first gate insulation film; a second gate insulation film provided on the floating gate electrode; a control gate electrode provided on the second gate insulation film; a source layer and a drain layer that are provided in the semiconductor substrate, the source layer and the drain layer respectively being provided either side of a channel region which is below the floating gate electrode; a source electrode that is electrically connected to the source layer; a buffer film provided on the drain layer; and a memory cell including a drain electrode electrically connected to the drain layer through the buffer film, wherein when viewing the surface of the semiconductor substrate from above, an overlapped area between the floating gate electrode and the drain layer is smaller than an overlapped area between the floating gate electrode and the source layer.

1 . A method of manufacturing a semiconductor memory device that comprises a memory cell which stores electric charges into a floating gate electrode or discharges electric charges from the floating gate electrode through a channel region between a source region and a drain region under control of a control gate electrode, a plurality of the memory cells being arranged adjacently each other in a channel length direction by sandwiching the source region or the drain region, the method comprising:
 laminating a first gate insulation film, a floating gate material, a second gate insulation film, and a control gate material on a semiconductor substrate sequentially in this order;   etching the first gate insulation film, the floating gate material, the second gate insulation film, and the control gate material on each region of the source and the drain, thereby forming the floating gate electrode and the control gate electrode;   depositing a buffer film made of an insulation material on the semiconductor substrate;   etching the buffer film on the source region while leaving the buffer film on the drain region; and   introducing impurities into the source region and the drain region.   
   
   
       2 . The method of manufacturing a semiconductor memory device according to  claim 1 , wherein
 the buffer film consists of a high dielectric insulation film having a higher dielectric constant than that of a silicon oxide film.   
   
   
       3 . The method of manufacturing a semiconductor memory device according to  claim 1  further comprising:
 forming a sidewall insulation film that covers sidewalls of the floating gate electrode and the control gate electrode, respectively, after forming the floating gate electrode and the control gate electrode, wherein   the buffer film is made of an insulation material having an etching rate different from an insulation material of the sidewall insulation film.   
   
   
       4 . The method of manufacturing a semiconductor memory device according to  claim 3 , wherein
 the semiconductor memory device is a NOR flash memory.   
   
   
       5 . A method of manufacturing a semiconductor memory device that has a memory cell which stores electric charges into a floating gate electrode or discharges electric charges from the floating gate electrode through a channel region between a source region and a drain region under control of a control gate electrode, a plurality of the memory cells being arranged adjacently each other in a channel length direction by sandwiching the source region or the drain region, the method comprising:
 laminating a first gate insulation film, a floating gate material, a second gate insulation film, and a control gate material on a semiconductor substrate sequentially in this order;   etching the first gate insulation film, the floating gate material, the second gate insulation film, and the control gate material on each region of the source and the drain, thereby forming laminated bodies each consisting of the first gate insulation film, the floating gate electrode, the second gate insulation film, and the control gate electrode, such that an interval between the laminated bodies adjacently disposed to sandwich the drain region is smaller than an interval between the laminated bodies adjacently disposed to sandwich the source region;   depositing a buffer film made of an insulation material between the adjacent laminated bodies;   depositing a masking insulation film having an etching rate different from that of the buffer film, thereby filling the masking insulation film into the interval between the laminated bodies on the drain region, without filling the masking insulation film into the interval between the laminated bodies on the source region;   anisotropically etching the masking insulation film, thereby exposing the buffer film on the source region while keeping the buffer film on the drain region covered with the masking insulation film;   etching the buffer film on the source region in self alignment while leaving the buffer film on the drain region by using the masking insulation film as a mask; and   introducing impurities into the source region and the drain region.   
   
   
       6 . The method of manufacturing a semiconductor memory device according to  claim 5 , wherein
 after forming the source and the drain by annealing, when viewing the surface of the semiconductor substrate from above, an overlapped area between the floating gate electrode and the drain layer is smaller than an overlapped area between the floating gate electrode and the source layer.   
   
   
       7 . The method of manufacturing a semiconductor memory device according to  claim 5 , wherein
 assuming that a film thickness of the masking insulation film is T 21 , that an interval between the laminated bodies sandwiching the source region is LGS, and that an interval between the laminated bodies sandwiching the drain region is L GD ,
     L   GD /2 <T   21   <L   GS /2  (Expression 1) 
   
     the film thickness T 21  satisfies the expression 1. 
   
   
       8 . The method of manufacturing a semiconductor memory device according to  claim 5  further comprising:
 forming a sidewall insulation film to cover sidewalls of the laminated bodies, wherein   assuming that a film thickness of the masking insulation film is T 21 , that an interval between the laminated bodies sandwiching the source region is L GS , that an interval between the laminated bodies sandwiching the drain region is L GD , and that a film thickness of the sidewall insulation film is T 40 ,
   (( L   GD /2)− T   40 )< T   21 <(( L   GS /2)− T   40 )  (Expression 2) 
   
     the film thickness T 21  satisfies the expression 1. 
   
   
       9 . The method of manufacturing a semiconductor memory device according to  claim 5 , wherein
 the buffer film consists of a high dielectric insulation film having a higher dielectric constant than that of a silicon oxide film.   
   
   
       10 . The method of manufacturing a semiconductor memory device according to  claim 5 , wherein
 the semiconductor memory device is a NOR flash memory.