Structure for optimizing fill in semiconductor features deposited by electroplating

Abstract

A structure and process are provided that are capable of reducing the occurrence of discontinuities within the metallization, such as voiding or seams, formed during electroplating at the edges of semiconductor metallization arrays. The structure includes a metallization bar located around the periphery of the array. The process employs the structure during electroplating.

1 . A structure capable of reducing the occurrence of discontinuities within the metallization that form during electroplating at the edges of semiconductor arrays which comprises a substrate having a semiconductor array comprising conductive lines and a metallization bar located around the periphery of the array, and dielectric material located between the metallization bar and semiconductor array to form a gap between the bar and array. 
   
   
       2 . The structure of  claim 1  wherein the gap is about 0.5 μm to about 2 μm in width. 
   
   
       3 . The structure of  claim 1  wherein the gap is about 1 μm to about 2 μm in width. 
   
   
       4 . The structure of  claim 1  wherein the bar has a width larger than that of the array. 
   
   
       5 . The structure of  claim 1  wherein the bar has a width of about 1 μm or less. 
   
   
       6 . The structures of  claim 1  wherein the bar is at least about 2 times larger than the width of the array lines. 
   
   
       7 . The structure of  claim 1  wherein the thickness of the bar is substantially the same as the thickness of the array lines. 
   
   
       8 . The structure of  claim 1  wherein the semi-conductor array and metallization bar have the same constituents. 
   
   
       9 . The structure of  claim 8  wherein the semiconductor array and metallization bar comprises a barrier layer located beneath a conductive layer. 
   
   
       10 . The structure of  claim 1  wherein the bar contains a break around the periphery of the array. 
   
   
       11 . The structure of  claim 1  wherein the bar is connected to a ground potential. 
   
   
       12 . A method for electroplating an array of electrically conductive material onto a conductive seed layer or directly onto a platable resistive metal barrier layer located on a substrate which comprises:
 plating a metallization bar on the substrate around the periphery where the array of electrically conductive material is to be located;   contacting the substrate with a plating bath that optionally comprises a super filling additive and a suppressor, applying a current or voltage across electrodes, wherein the substrate acts as one electrode and a conductor acts as a counter electrode to plate the electrically conductive material on the substrate.   
   
   
       13 . The method of  claim 12  wherein the array and bar are plated at the same time. 
   
   
       14 . The method of  claim 12  wherein the gap is about 0.5 μm to about 2 μm in width. 
   
   
       15 . The method of  claim 12  wherein the gap is about 1 μm to about 2 μm in width. 
   
   
       16 . The method of  claim 12  wherein the bar has a width larger than that of the array. 
   
   
       17 . The method of  claim 12  wherein the bar has a width of about 1 μm or less. 
   
   
       18 . The method of  claim 12  wherein the bar is at least about 2 times larger than the width of the array lines. 
   
   
       19 . The method of  claim 12  wherein the thickness of the bar is substantially the same as the thickness of the array lines. 
   
   
       20 . The method of  claim 1  wherein the semi-conductor array and metallization bar have the same constituents. 
   
   
       21 . The method of  claim 20  wherein the semiconductor array and metallization bar comprises a barrier layer located beneath a conductive layer. 
   
   
       22 . The method of  claim 1  wherein the bar contains a break around the periphery of the array. 
   
   
       23 . The method of  claim 1  wherein the bar is connected to a ground potential.