Transistor having gate dielectric layer of partial thickness difference and method of fabricating the same

Abstract

A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick thickness formed on both sides of the main portion. A first gate is formed overlapping the main portion of the gate dielectric layer, and forming a second gate layer covering the sidewall portion of the gate dielectric layer and covering the first gate. The second gate layer is etched, thereby forming second gates patterned with a spacer shape on sidewalls of the first gate. The exposed sidewall portion of the gate dielectric layer is selectively etched using the second gates as a mask, thereby forming a pattern of the gate dielectric layer to be aligned with the second gates. A source/drain is formed in a portion of the semiconductor substrate exposed by the second gates.

1 . A transistor comprising:
 a semiconductor substrate;   a first dielectric layer formed on the semiconductor substrate;   a first gate formed on the first dielectric layer to overlap the first dielectric layer;   inner spacers formed on sidewalls of the first gate;   second gates formed on sidewalls of the first gate with a spacer shape on the inner spacers;   a second dielectric layer formed to be self-aligned with the second gates and having a thicker thickness than that of the first dielectric layer; and   a source/drain formed in a portion of the semiconductor substrate exposed by the second gates.   
   
   
       2 . The transistor according to  claim 1 , further comprising:
 a gate electrode including a silicide layer connected to the gate; and   source/drain electrodes including a silicide layer connected to the source/drain.   
   
   
       3 . The transistor according to  claim 1 , wherein the gate electrode is selectively connected to the first gate, and the first gate is insulated from the second gates by the inner spacers. 
   
   
       4 . The transistor according to  claim 1 , wherein two of the second gates on both sides of the first gate are formed with equal widths to be self-aligned with the first gate. 
   
   
       5 . The transistor according to  claim 4 , wherein the source/drain comprises:
 a first impurity layer formed by performing an ion implantation process using two of the second gates having equal widths as a mask, a width of the portion of the first impurity layer overlapping the second gates being controlled by the second gates; and   a second impurity layer formed by performing an ion implantation process using spacers attached to the second gates as a mask and aligned with the spacers.   
   
   
       6 . The transistor according to  claim 1 , wherein the semiconductor substrate comprises a recess groove to form a recess channel overlapping the first gate;
 the inner spacers extend to cover sidewalls of the recess groove;   the first dielectric layer is disposed at a bottom of the recess groove; and   the first gate fills the recess groove.