Method and system for designing a flexible hardware state machine

Abstract

Method and system for performing hardware tasks using a hardware state machine and a processor is provided. The method includes, setting a breakpoint for a state machine state; running the processor in a parallel mode with the state machine; passing control to the processor after a breakpoint condition is encountered; performing a task, wherein the processor performs the task which was meant to be performed by the state machine; and transferring control back to the state machine after the processor performs the task. The system includes an Application Specific Integrated Circuit (ASIC) with the state machine, and the processor.

1 .- 13 . (canceled) 
   
   
       14 . A method for performing hardware tasks in an application specific integrated circuit (ASIC) with a hardware state machine and a processor, the method comprising:
 the state machine transitioning to a current state;   the state machine reading a control register to determine whether a breakpoint is set for the current state;   where the breakpoint is set for the current state, transferring control to the processor via a status register;   the processor performing a task that the state machine was intended to perform;   after the task is completed, the processor setting a status bit in the status register; and   transferring control back to the state machine;   wherein the ASIC comprises the hardware state machine and the processor in a single component.   
   
   
       15 . The method of  claim 14 , further comprising programming the control register with breakpoint information for individual states of the state machine. 
   
   
       16 . The method of  claim 14 , further comprising the status register storing a status of each of a plurality of tasks, each task corresponding to a state of the state machine. 
   
   
       17 . The method of  claim 14 , wherein the breakpoint is set for any or all states of the state machine. 
   
   
       18 . The method of  claim 14 , wherein the state machine reads the control register each time the state machine transitions from a first state to a second state to determine if a breakpoint is set for the second state. 
   
   
       19 . The method of  claim 14 , wherein the processor for the ASIC is an embedded processor. 
   
   
       20 . The method of  claim 14 , further comprising setting additional breakpoint conditions for a plurality of additional states for a plurality of additional state machines, and the processor performs a plurality of additional tasks associated with the plurality of additional states. 
   
   
       21 . An application specific integrated circuit (ASIC), comprising:
 a hardware state machine configured to execute a plurality of tasks associated with a plurality of states;   a random access memory (RAM);   a processor configured to control the state machine and to execute instructions from images loaded into the RAM;   a control register programmed with breakpoint information for at least one of the states; and   a status register;   wherein when the state machine transitions to a current state, it is configured to read the control register to determine whether a breakpoint is set for the current state, and where the breakpoint is set for the current state control is transferred to the processor via the status register, and the processor is configured to perform a task that the state machine was intended to perform; and   wherein the ASIC comprises the hardware state machine and the processor in a single component.   
   
   
       22 . The ASIC of  claim 21 , wherein the processor is configured to set a status bit in the status register after the task is completed. 
   
   
       23 . The ASIC of  claim 21 , wherein control is transferred back to the state machine after the task is completed. 
   
   
       24 . The ASIC of  claim 21 , wherein a breakpoint condition is set for any or all states of the state machine. 
   
   
       25 . The ASIC of  claim 21 , wherein the state machine is configured to read the control register each time the state machine transitions from a first state to a second state to determine if a breakpoint is set for the second state. 
   
   
       26 . The ASIC of  claim 21 , wherein the processor is an embedded processor.