Cmos device with dual polycide gates and method of manufacturing the same

Abstract

A CMOS device having dual polycide gates is formed by first providing a silicon substrate, which is divided into a cell area and a peripheral circuit area and has a device isolation layer, a P-well, and a N-well in the peripheral circuit area. The n+ polycide gate at the P-well and the p+ polycide gate at the N-well are formed. An interlayer dielectric layer is formed on the resultant of the silicon substrate having the n+ polycide gate and the p+ polycide gate. A first bit-line contact hole for exposing the n+ polycide gate is formed, and a second bit-line contact hole for exposing the p+ polycide gate is formed. Bit-lines with a bridge structure on the interlayer dielectric layer is formed. The bit-lines simultaneously contact the n+ polycide gate and the p+ polycide gate through the first and second bit-line contact holes.

1 . A method of manufacturing a CMOS device having a dual polycide gate structure, the method comprising the steps of:
 providing a silicon substrate, which is divided into a cell area and a peripheral circuit area, having a device isolation layer between a P-well region and a N-well region in the peripheral circuit area;   forming a n+ polycide gate having at least a first metal silicide layer at the P-well region and a p+ polycide gate having at least a second metal silicide layer at the N-well region, wherein the n+ polysilicon gate and the p+ polysilicon gate are separated from each other;   forming an interlayer dielectric layer on the n+ polycide gate and on the p+ polycide gate and on the substrate between the separated n+ and p+ polycide gates;   forming a first bit-line contact hole for exposing the n+ polycide gate through the interlayer dielectric layer and a second bit-line contact hole for exposing the p+ polycide gate through the interlayer dielectric layer; and   forming a bit-line having a first end and a second end formed on the interlayer dielectric layer, wherein the first end is connected to the n+ polycide gate and the second end is connected to the p+ polycide gate such that a bridge structure is formed on the interlayer dielectric layer, the bit-lines simultaneously contacting with the n+ polycide gate and the p+ polycide gate, which are separated from each other, through the first and second bit-line contact holes.   
   
   
       2 . The method of  claim 1 , wherein the step of forming the n+ polycide gate and the p+ polycide gate comprises the sub-steps of:
 forming a gate insulation layer and a silicon layer on the substrate, sequentially;   selectively ion-implanting n-type impurity in a portion of the silicon layer formed at the P-well region in the peripheral area of the substrate, while selectively ion-implanting p-type impurity in a portion of the silicon layer formed at the N-well region in the peripheral area of the substrate;   sequentially forming the metal silicide layer and the hard mask layer on the silicon layer of each region in which the n-type and p-type impurities are ion-implanted; and   etching the hard mask layer, the metal silicide layer, the silicon layer, and the gate insulation layer, wherein the portion of the metal silicide layer formed on the P-well region is the first metal silicide layer and the portion of the metal silicide layer formed on the N-well region is the second metal silicide layer.   
   
   
       3 . The method of manufacturing a CMOS device as claimed in  claim 2 , wherein the silicon layer is formed in an armorphos state. 
   
   
       4 . The method of manufacturing a CMOS device as claimed in  claim 2 , wherein the n-type impurity ion implant is performed by using Phosphorus or Arsenic. 
   
   
       5 . The method of manufacturing a CMOS device as claimed in  claim 2 , wherein the p-type impurity ion implant is performed by using Boron or Boron difluoride. 
   
   
       6 . The method of manufacturing a CMOS device as claimed in  claim 1 , wherein the metal silicide layer is formed with a tungsten silicide layer.