Bi-directional single wire interface

Abstract

A single-wire, bi-directional communication protocol is provided in which the sending device transmits its clock frequency and its bit transmission period and data through a predefined waveform pattern or “learning sequence” that is recognizable by the receiving device and in a period of time, as measured in number of sending clock cycles, that is known to the receiving device. By clocking the full length of the predefined waveform pattern using its own internal clock, the receiving device becomes aware of the bit transmission period of the sending device.

1 . An apparatus, comprising:
 a first device operating at a first clock frequency, the first device to transmit a learning sequence with a predetermined waveform pattern and a predetermined duration that represents a length of time, based on the first clock frequency; and   a second device to receive the learning sequence and analyze the learning sequence to discover the clock frequency of the first device to adjust a sampling frequency based upon the discovered clock frequency.   
   
   
       2 . The apparatus of  claim 1 , wherein the learning sequence is preceded by a start sequence that signifies a beginning of a transmission and provides a synchronization point. 
   
   
       3 . The apparatus of  claim 2 , wherein the first device is configured to maintain a first voltage level while communication is idle and initiate the start sequence where the start sequence comprises a waveform at a different voltage level held for at least two clock cycles. 
   
   
       4 . The apparatus of  claim 1 , wherein the learning sequence comprises a waveform with a first period of a first voltage level and a second period of a second voltage level. 
   
   
       5 . The apparatus of  claim 4 , wherein the first voltage level is held for a longer time than the second voltage level. 
   
   
       6 . The apparatus of  claim 5 , wherein the first period of first voltage level takes up about 80% of the duration of the learning sequence while the second period of second voltage level takes up about 20% of the duration of the learning sequence. 
   
   
       7 . The apparatus of  claim 4 , wherein the first voltage level is higher than the second voltage level. 
   
   
       8 . The apparatus of  claim 4 , wherein a subsequent signal transmission by a sending device has the first voltage level with a duration that is longer than a duration of the second voltage level for a representation of logic “1,” while a duration of the first voltage level is shorter than a duration of the second voltage level for a representation of logic “0.” 
   
   
       9 . A bi-directional single wire data communication system, comprising:
 a master device having a first clock running at a first frequency; and   a slave device having a second clock running at a second frequency, wherein the master device and the slave device are communicatively coupled, and the master sends a first command sequence that notifies the slave device of an intent to read, and the slave device sends in response, a learning sequence with a predetermined waveform pattern and a predetermined duration that represents a length of time, based on the clock in the slave device, for transmitting a single bit; and   wherein the master device initiates a counting routine having a duration, in number of clock cycles, of the learning sequence is measured based on the first clock in the master device.   
   
   
       10 . The system of  claim 9 , wherein the master device sends a second command sequence that notifies the slave device of an intent to write, sends a data sequence which comprises a plurality of data bits, wherein at least one of the plurality of data bits has a predetermined waveform pattern and a predetermined duration based on the first clock in the master device. 
   
   
       11 . The system of  claim 10 , wherein the first and second command sequence is preceded by a start sequence that signifies the beginning of a transmission and provides a synchronization point. 
   
   
       12 . The system of  claim 9  configured to provide a one time power-up reset sequence when the slave device is connected to the master device. 
   
   
       13 . The system of  claim 10 , configured to have the first and second command sequences include addresses of memory to which the master device reads from or writes to respectively. 
   
   
       14 . The system of  claim 12 , wherein the master device sends a reset pulse and the slave device receives the reset pulse and replies with the start sequence and the learning sequence during a power-up reset sequence. 
   
   
       15 . The system of  claim 10 , configured to have the learning sequence and at least one of the plurality of data bits represented by a waveform having a first voltage level followed by a second voltage level. 
   
   
       16 . The system of  claim 15 , wherein the learning sequence has the first voltage level that is held for a longer time period than the second voltage level. 
   
   
       17 . The system of  claim 16 , wherein the time period at the first voltage level takes up about 80% of the duration of the learning sequence, while the time period at the second voltage level takes up about 20% of the duration of the learning sequence. 
   
   
       18 . The system of  claim 17 , wherein the first voltage level is higher than the second voltage level. 
   
   
       19 . The system of  claim 15 , wherein at least one of the plurality of data bits has a first voltage level with a duration that is longer than a duration of the second voltage level for the representation of logic “1,” while a duration of the first voltage level is shorter than a duration of the second voltage level for the representation of logic “0.” 
   
   
       20 . The system of  claim 19 , wherein at least one of the plurality of data bits is rejected if a duration of a data bit as measured by the clock in the slave device is less than a first preset number or more than a second preset number, with the first preset number being less than the second preset number. 
   
   
       21 . The system of  claim 10 , wherein the first and the second command sequences are a byte of data including a single bit that indicates a desired operation and a plurality of bits that indicates a memory location on which to operate.