Production of a Transistor Gate on a Multibranch Channel Structure and Means for Isolating This Gate From the Source and Drain Regions

Abstract

A method for fabricating a microelectronic device including a support, an etched stack of thin layers including at least one first block and at least one second block resting on the support, in which at least one drain region and at least one source region, respectively, are capable of being formed, plural semiconductor bars connecting a first zone of the first block and another zone of the second block, and able to form a multi-branch transistor channel, or plural transistor channels. A gate surrounds the bars and is located between the first block and the second block, the gate being in contact with a first and second insulating spacer in contact with at least one sidewall of the first block and with at least one sidewall of the second block, respectively, and at least partially separated from the first block and the second block, via the insulating spacers.

1 - 25 . (canceled) 
   
   
       26 . A microelectronic device comprising:
 a support;   an etched stack of thin layers comprising at least one layer based on a first semiconductor material, and at least one layer based on a second semiconductor material different from the first material, the stack resting on the support and comprising at least one first block and at least one second block, wherein at least one drain region and at least one source region are capable of being formed, respectively, one or plural semiconductor bars connecting a first zone of the first block and another zone of the second block, and capable of forming a transistor channel or a multi-branch transistor channel, or plural transistor channels;   a gate located between the first block and the second block, at least partially surrounding the bars;   at least one first insulating zone formed against at least one sidewall of the first block; and   at least one second insulating zone across from the first insulating zone, and formed against at least one sidewall of the second block, the gate being in contact with the first insulating zone and the second insulating zone and at least partially separated from the first block and the second block, via the first and second insulating zones.   
   
   
       27 . The microelectronic device according to  claim 26 , at least one bar among the bars being suspended above the support between the first block and the second block, and/or being separated from the support. 
   
   
       28 . The microelectronic device according to  claim 26 , at least two of the semiconductor bars being aligned in a direction parallel to the primary plane of the support. 
   
   
       29 . The microelectronic device according to  claim 26 , at least two of the semiconductor bars being separated, and aligned in a direction fabricating a non-null angle with the primary plane of the support. 
   
   
       30 . The microelectronic device according to  claim 26 , the stack being formed of an alternation of layers based on a first semiconductor material and layers based on a second material, different from the first semiconductor material. 
   
   
       31 . The microelectronic device according to  claim 26 , the first insulating zone and the second insulating zone being spaced, between the first block and the second block, by a constant distance equal to a critical dimension of the gate. 
   
   
       32 . The microelectronic device according to  claim 26 , the first material or the second material being based on a semiconductor comprising an additive. 
   
   
       33 . A method for fabricating a microelectronic device comprising:
 a) forming, from a stack of thin layers on a support, the stack including at least two successive layers based on at least one first semiconductor material, and at least one second semiconductor material different from the first semiconductor material, respectively: at least one first block configured to form at least one transistor source region, at least one second block configured to form at least one transistor drain region, and at least one structure connecting the first block and the second block;   b) forming, in a region located between the first block and the second block, at least one first insulating zone against at least one sidewall of the first block and at least one second insulating zone against at least one sidewall of the second block, and at least one cavity between the first insulating zone and the second insulating zone, the cavity comprising or forming at least one gate pattern;   c) removing, in the cavity, the second material, selective with regard to the first material; and   d) depositing in the cavity at least one gate dielectric and at least one gate material.   
   
   
       34 . The method according to  claim 33 , wherein the cavity also includes at least one transistor gate contact pattern. 
   
   
       35 . The method according to  claim 33 , further comprising, after d), forming at least one transistor gate contact through etching of the gate material. 
   
   
       36 . The method according to  claim 33 , the forming the insulating zones in b) comprising:
 depositing a layer based on a dielectric material on the support; and   exposing part of the layer of dielectric material using an electron beam.   
   
   
       37 . The method according to  claim 36 , the layer of dielectric material being based on an HSQ dielectric, the forming the insulating zones in b) further comprising, after the exposing, removing the zones of the HSQ dielectric material not exposed to the electron beam. 
   
   
       38 . The method according to  claim 33 , the structure being formed of at least two separated blocks. 
   
   
       39 . The method according to  claim 33 , in which the support includes a dielectric layer on which the stack is formed, the method further comprising: after the forming b), and before the depositing d), partially removing the dielectric layer of the support through the cavity. 
   
   
       40 . The method according to  claim 33 , the stack being formed by an alternation of layers based on the second material and layers based on the first material. 
   
   
       41 . The method according to  claim 33 , the stack including a layer based on the second material in contact with the support. 
   
   
       42 . The method according to  claim 33 , the depositing d) comprising depositing at least one layer of a first metallic gate material on the gate dielectric, then filling the cavity with at least one second semiconductor gate material. 
   
   
       43 . The method according to  claim 33 , the first material or the second material being based on a semiconductor including an additive. 
   
   
       44 . The method according to  claim 33 , the first insulating zone and the second insulating zone being separated, between the first block and the second block, by a constant distance equal to a critical dimension of a gate designed to be formed in the cavity. 
   
   
       45 . The method according to  claim 33 , in which the insulating zones are formed to rest on the support. 
   
   
       46 . The method according to  claim 33 , further comprising at least one operation for doping of the first block and the second block. 
   
   
       47 . A method for fabricating a microelectronic device comprising:
 a) forming from a stack of thin layers on a support, the stack including at least two successive layers based on at least one first semiconductor material, and at least one second material different from the first material, respectively: at least one first block configured to form at least one transistor source region and at least one second block configured to form at least one transistor drain region, and at least one structure connecting the first block and the second block;   b) forming on the stack, an insulating mask including at least one cavity, the cavity including at least one transistor gate pattern;   c) removing through the cavity the second material, selective with regard to the first semiconductor material;   d) depositing in the cavity at least one gate dielectric and at least one gate material; and   e) partially removing the insulating mask, so as to preserve at least one first insulating zone resulting from the mask, in contact with the gate material and at least one sidewall of the first block, as well as at least one second insulating zone resulting from the mask, in contact with the gate material and with at least one sidewall of the second block, the gate material being at least partially separated from the first block and the second block via the first insulating zone and the second insulating zone, respectively.   
   
   
       48 . The method according to  claim 47 , the partially removing in e) comprising partial etching of the insulating mask above the first block, the second block, as well as the structure connecting the first block and the second block. 
   
   
       49 . The method according to  claim 48 , wherein the b) forming an insulating mask provided with at least one cavity, comprises:
 depositing a first dielectric material;   lithography of the first dielectric material using at least one electron beam, so as to form at least one transistor gate pattern;   forming a second material, on both sides of the base pattern of the first dielectric material; and   removing the pattern based on the first dielectric material.   
   
   
       50 . The method according to  claim 49 , the first dielectric material being an HSQ material.