Processing apparatus

Abstract

A processing apparatus which executes a program and performs processes of the program, includes an execution circuit including a plurality of central processing units, each having a respective cache memory, and each of the respective cache memories has an N-way set-associative structure with N-ways in which one line is made up of plural words. Each of the respective cache memories includes a data memory array which is simultaneously read-out in multiple-word-widths, and can be read-out using one of a type one read-out and a type two read-out. In the type one read-out, plural words in the same word positions within respective lines are simultaneously read-out from corresponding lines belonging to different ways, and in the type two read out, plural words making up one line of one way are simultaneously read-out. The cache memory has a first read-out mode and a second read-out mode. In the first read-out mode, a word belonging to a way which is hit by a memory access is selected from among the plural words read-out using the type-one read out, and the selected word is outputted, and in the second read-out mode, plural words are read-out from a way which is hit, using the type-two read out, and read-out plural words are outputted.

1 . A processing apparatus which executes a program and performs processes of the program, said processing apparatus comprising
 an execution circuit including a plurality of central processing units, each having a respective cache memory,   wherein each of said respective cache memories has an N-way set-associative structure with N-ways in which one line is made up of plural words,   each of said respective cache memories is made up of a data memory array which is simultaneously read-out in multiple-word-widths,   said data memory array can be read-out using one of a type one read-out and a type two read-out,   in the type one read-out, plural words in the same word positions within respective lines are simultaneously read-out from corresponding lines belonging to different ways,   in the type two read out, plural words making up one line of one way are simultaneously read-out,   said cache memory has a first read-out mode and a second read-out mode,   in the first read-out mode, a word belonging to a way which is hit by a memory access is selected from among the plural words read-out using the type-one read out, and the selected word is outputted,   in the second read-out mode, plural words are read-out from a way which is hit, using the type-two read out, and read-out plural words are outputted,   the first read-out mode is used in the case where the plurality of said central processing units accesses said respective cache memories, and   the second read-out mode is used in the case where data is transmitted between respective cache memories of said plurality of central processing units.   
   
   
       2 . The processing apparatus according to  claim 1 ,
 wherein said data memory array is made up of a plurality of SRAM memories which can be read-out in word-widths.   
   
   
       3 . The processing apparatus according to  claim 2 ,
 wherein said data memory array is made up of one or more SRAM memories which can be read-out in multiple word-widths, each of the SRAM memories is made up of plural columns, and the SRAM memory receives a signal separately for each of the words, the signal controlling selection of the columns.