Method of detecting and recovering a lost system management interrupt (smi) in a multiprocessor (mp) environment

Abstract

Method, computer program product and system for handling multiple system management interrupt (SMI) events in a multiprocessor system. In response to receiving an SMI event, processors enter system management mode (SMM) and execute SMI handler code. An SMI handler that determines fewer than all of the processor are in the SMI handler for the event will schedule an further SMI event based upon the content of the detected SMI event, then issues a resume (RSM) instruction and exits the SMI handler. The method recovers lost SMI events caused by latency between multiple processors entering or exiting SMM.

1 - 9 . (canceled) 
   
   
       10 . A computer program product including computer useable program code embodied on a computer usable medium, the computer program product including:
 computer usable program code for receiving a first SMI event;   computer usable program code for entering an SMI handler for the first SMI event; and   computer usable program code for determining that fewer than all of the active processors in the multiprocessor system are in the SMI handler for the first SMI event; then   scheduling a second SMI event based upon the content of the first SMI event; and then   exiting the SMI handler for the first SMI event without handling the first SMI event.   
   
   
       11 . The computer program product of  claim 10 , wherein the computer usable program code for determining that fewer than all of the active processors in the multiprocessor system are in the SMI handler for the first SMI event includes computer usable program code for waiting for a period of time before scheduling the second SMI event, wherein the period of time has a duration sufficient to allow processors to enter the SMI handler for the first SMI event under typical conditions had the first SMI event been received. 
   
   
       12 . The computer program product of  claim 10 , further comprising
 computer usable program code for handling the second SMI event as a result of determining that all of the active processors in the multiprocessor system are in the SMI handler for the second SMI event.   
   
   
       13 . The computer program product of  claim 10 , further comprising
 computer usable program code for exiting the SMI handler for the first SMI event before the occurrence of the second SMI event.   
   
   
       14 . The computer program product of  claim 13 , further comprising:
 computer usable program code for entering into the SMI handler for a third SMI event that was pending while the processors were in the SMI handler for the first SMI event; and   computer usable program code for handling the third SMI event so long as all of the active processors in the multiprocessor system are in the SMI handler for the third SMI event.   
   
   
       15 . The computer program product of  claim 10 , further comprising computer usable program code for exiting the SMI handler for the first SMI event before the occurrence of the second SMI event if the SMI handler has a pending SMI event at the time that the second SMI event is being scheduled. 
   
   
       16 . The computer program product of  claim 10 ,
 further comprising computer usable program code for scheduling an additional SMI event for an SMI event that is pending at the time that the second SMI event is being scheduled, wherein the additional SMI is based upon the content of the pending SMI event; and   computer usable program code for cancelling the pending SMI event without handling the pending SMI event.   
   
   
       17 . A computer system, comprising:
 multiple processors configured for receiving a system management interrupt event;   an SMI handler associated with one or more of the processors for processing system management interrupt;   a logic structure for a first set of one or more processors in the multiprocessor system receiving a first SMI event;   a logic structure for the first set of processors entering an SMI handler for the first SMI event;   a logic structure for determining that fewer than all of the active processors in the multiprocessor system are in the SMI handler for the first SMI event;   a logic structure for scheduling a second SMI event based upon the content of the first SMI event; and   a logic structure for the first set of processors each exiting the SMI handler for the first SMI event without handling the first SMI event.   
   
   
       18 . The computer system of  claim 17 , wherein the logic structure for determining that fewer than all of the active processors in the multiprocessor system are in the SMI handler for the first SMI event includes a logic structure to wait for a period of time before scheduling the second SMI event, wherein the period of time has a duration sufficient to allow processors to enter the SMI handler for the first SMI event under typical conditions had the first SMI event been received. 
   
   
       19 . The computer system of  claim 17 , further comprising:
 a logic structure for handling the second SMI event as a result of determining that all of the active processors in the multiprocessor system are in the SMI handler for the second SMI event.   
   
   
       20 . The computer system of  claim 17 , wherein the first set of processors each exit the SMI handler for the first SMI event before the occurrence of the second SMI event.