US2008276021A1PendingUtilityA1

Data transfer control apparatus

Assignee: RENESAS TECH CORPPriority: Apr 14, 2003Filed: Jun 3, 2008Published: Nov 6, 2008
Est. expiryApr 14, 2023(expired)· nominal 20-yr term from priority
Y02D10/00G06F 13/4226
49
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A data transfer control apparatus has a plurality of bus slaves connected to a bus master via a bus interface unit for RAM connected to the bus master via a master bus, and a transfer bus which connects the first bus slave and plural second bus slaves in the plurality of bus slaves. When an instruction to execute data transfer via the transfer bus is given by a transfer instruction signal, data transfer between one second bus slave selected from the plural second bus slaves and the first bus slave via the transfer bus is carried out in response to a control signal contained in a control signal bus on a slave bus for RAM.

Claims

exact text as granted — not AI-modified
1 . A data processing apparatus comprising:
 a central processing unit;   a plurality of circuit modules; and   a bus including an address bus, a first data bus for transferring write data and a second bus for transferring read data,   wherein when the central processing unit sends data to one of the circuit modules, the central processing unit sends an address via the address bus for indicating which of the circuit modules is to be accessed, and sends data to said one of the circuit modules via the first data bus, and   wherein when the central processing unit receives data from one of the circuit modules, the central processing unit receives data via the second bus.   
   
   
       2 . A data processing apparatus according to  claim 1 ,
 wherein the second bus includes a third bus and a fourth bus,   wherein one of the plural circuit modules is a memory unit, and another one of the plural circuit modules is an IO unit,   wherein the third bus is used for transferring data from the memory unit to the central processing unit, and   wherein the fourth bus is used for transferring data from the IO unit to the central processing unit.   
   
   
       3 . A data processing apparatus according to  claim 2 , further comprising a first bus bridge and a second bus bridge,
 wherein the first bus bridge is located between the third bus and the memory unit, and the second bus bridge is located between the fourth bus and the IO unit.   
   
   
       4 . A data processing apparatus according to  claim 2 ,
 wherein a data transfer rate of the third bus is higher than that of the fourth bus.

Join the waitlist — get patent alerts

Track US2008276021A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.