Semiconductor device and method of forming the same

Abstract

A semiconductor device includes a first gate structure including a gate dielectric layer directly contacting the substrate, a bottom electrode on the gate dielectric layer and a top electrode on the bottom electrode, and a second gate structure including a gate dielectric layer directly contacting the substrate and a gate electrode on the gate dielectric layer.

1 . A semiconductor device, comprising:
 a substrate;   a first gate structure on said substrate, comprising:
 a gate dielectric directly contacting said substrate; 
 a lower electrode on said gate dielectric; and 
 an upper electrode on said lower electrode; 
   a first source/drain in the proximity of said first gate structure;   a second gate structure on said substrate, comprising said gate dielectric directly contacting said substrate and a gate electrode on said gate dielectric;   a second source/drain in the proximity of said second gate structure; and   an interlayer dielectric covering said substrate, said first gate structure, said first source/drain, said second gate structure and said second source/drain.   
   
   
       2 . The semiconductor device of  claim 1 , wherein said substrate is selected from the group consisting of silicon, direct-silicon bonding, silicon on insulator, and silicon on insulator direct silicon bonding. 
   
   
       3 . The semiconductor device of  claim 1 , wherein said lower electrode has a thickness of 10-300Å. 
   
   
       4 . The semiconductor device of  claim 1 , wherein said upper electrode comprises a silicide. 
   
   
       5 . The semiconductor device of  claim 1 , wherein said first source/drain comprises a silicide. 
   
   
       6 . The semiconductor device of  claim 4 , wherein said gate electrode comprises a silicide. 
   
   
       7 . The semiconductor device of  claim 1 , wherein said second source/drain comprises a silicide. 
   
   
       8 . The semiconductor device of  claim 1 , wherein said first gate structure is a P-channel metal-oxide semiconductor gate structure and said second gate structure is an N-channel metal-oxide semiconductor gate structure. 
   
   
       9 . The semiconductor device of  claim 8 , wherein said lower electrode comprises a conductive material with a work function smaller than that of said substrate. 
   
   
       10 . The semiconductor device of  claim 8 , wherein said lower electrode comprises titanium nitride. 
   
   
       11 . The semiconductor device of  claim 8 , wherein said gate electrode comprises a Ni-rich silicide. 
   
   
       12 . The semiconductor device of  claim 1 , wherein said first gate structure is an N-channel metal-oxide semiconductor gate structure and said second gate structure is a P-channel metal-oxide semiconductor gate structure. 
   
   
       13 . The semiconductor device of  claim 12 , wherein said lower electrode comprises a conductive material with a work function higher than that of said substrate. 
   
   
       14 . The semiconductor device of  claim 12 , wherein said lower electrode comprises a group consisting of MCx, MBx, MCxNy, MBxNy and MBxCy, where M is a metal of (III) group to (VII) group. 
   
   
       15 . The semiconductor device of  claim 12 , wherein said lower electrode comprises TaC. 
   
   
       16 . The semiconductor device of  claim 12 , wherein said gate electrode comprises a Si-rich silicide. 
   
   
       17 . The semiconductor device of  claim 16 , wherein said Si-rich silicide is nickel silicide. 
   
   
       18 . The semiconductor device of  claim 1 , wherein said nickel silicide is NiSi 2 . 
   
   
       19 . The semiconductor device of  claim 1 , further comprising a stress layer in the proximity of said first gate structure and said second gate structure. 
   
   
       20 . The semiconductor device of  claim 1 , wherein said interlayer dielectric comprise a plurality of contact holes exposing said first gate structure, said first source/drain, said second gate structure and said second source/drain. 
   
   
       21 - 42 . (canceled)