System and method for running test and redundancy analysis in parallel

Abstract

A memory redundancy analyzing apparatus having a tester, a queue, and a redundancy analyzer is provided. The tester includes testing portions for different types of fails, and each of the testing portions performs multiple tests on the memory locations and outputs fail information for at least a part of the memory device. The queue stores the fail information. The redundancy analyzer processes the fails using the fail information and produces a plurality of repair solutions. The types of fails include must fails and sparse fails. The fail information is transmitted to the queue, and the fail information includes at least a part of the fail information for the entire memory device. The tester can operate asynchronously from the redundancy analyzer.

1 . An apparatus for efficient test of a memory device comprising a main array and a plurality of redundant row and columns, each of which have a plurality of memory locations, the apparatus comprising:
 a tester configured to perform multiple test patterns on the plurality of memory locations and to generate fail information for at least a part of the memory locations;   a queue configured to receive the sparse fail information from the tester; and   a redundancy analyzer configured to process at least part of the plurality of fails received from the queue and configured to generate corresponding repair solutions;   wherein the tester is configured to proceed with a next test pattern before the redundancy analyzer processing the fail information from a previous test pattern.   
   
   
       2 . The apparatus of  claim 1 , wherein the tester further comprises a fail capture memory that receives the fail information from the tester. 
   
   
       3 . The apparatus of  claim 1 , wherein the redundancy analyzer is configured to manipulate the plurality of repair solutions. 
   
   
       4 . The apparatus of  claim 3 , wherein the redundancy analyzer changes a first repair solution for a sparse fail into a second repair solution to optimize the repair solution and to reduce the number of redundant rows and columns used in the repair solution. 
   
   
       5 . The apparatus of  claim 1 , further comprising a result storage unit configured to maintain at least part of the plurality of repair solutions previously evaluated from a previous test pattern, the result storage unit communicating with the redundancy analyzer. 
   
   
       6 . The apparatus of  claim 5 , wherein each of the plurality of repair solutions comprises addresses of fails and corresponding solutions, and wherein each of the plurality of repair solutions comprises information regarding disconnection of at least one fail and linkage of a plurality of redundant memory locations for replacement. 
   
   
       7 . The apparatus of  claim 1 , wherein the queue is implemented by software executed by a computer. 
   
   
       8 . The apparatus of  claim 1 , wherein the redundancy analyzer is configured to analyze sparse fails, further comprising a must redundancy analyzer configured to receive must fail information from the tester and configured to generate must fail solutions. 
   
   
       9 . The apparatus of  claim 8 , wherein the must redundancy analyzer is configured to proceed to process fail information from the next test pattern before the redundancy analyzer processing the fail information from the previous test pattern. 
   
   
       10 . The apparatus of  claim 9 , wherein the queue is configured to receive the repair solutions from the must redundancy analyzer. 
   
   
       11 . The apparatus of  claim 10 , wherein the redundancy analyzer is configured to receive at least part of the fails and the repair solutions from the queue. 
   
   
       12 . A method of repairing a memory device, the method comprising:
 applying a plurality of test patterns to a memory device to detect fails; and   performing a redundancy analysis for the detected fails in a parallel processing path asynchronous to applying the test patterns.   
   
   
       13 . The method of  claim 12 , wherein the plurality of test patterns comprise at least a first test pattern, a second test pattern, and a third test pattern, wherein the first test pattern is performed earlier in time than the second test pattern, and wherein the second test pattern is performed earlier in time than the third test pattern, further comprising: storing the fails from test patterns for access by the redundancy analysis process; and initiating the third test pattern before redundancy analysis for the first test pattern is complete. 
   
   
       14 . The method of  claim 13 , further comprising spawning a first thread for processing the fails from the test pattern and generates repair solutions, wherein the repair solutions comprise a plurality of must repair solutions. 
   
   
       15 . The method of  claim 14 , further comprising spawning a second thread for processing the fails from the test patterns and generates repair solutions, wherein the repair solutions comprise a plurality of sparse repair solutions. 
   
   
       16 . The method of  claim 15 , further comprising manipulating the must repair solutions and the sparse repair solutions to combine and optimize the repair solutions. 
   
   
       17 . The method of  claim 13 , wherein number of fails from each of the plurality of patterns diminishes as the number of the applied test patterns increases.