Semiconductor device and method of manufacturing the same
Abstract
A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals 6 G, 6 S via connection materials 5 b, 5 c . In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals 6 G, 6 S being exposed. Mounting surfaces of the metal plate terminals 6 G, 6 S and a third part of the metal cap are bonded to electrodes on a mounting board 10 via connection materials 5 e, 5 f and 5 g.
Claims
exact text as granted — not AI-modified1 .- 21 . (canceled)
22 . A method for manufacturing a semiconductor device comprising the steps of:
(a) providing a conductive cap having an upper part, a side part and a leg part; (b) mounting a semiconductor chip in a region enclosed by the upper part and the side part of the conductive cap,
the semiconductor chip having a first surface and a second surface opposite to each other, an upper electrode formed on the first surface, and first and second lower electrodes formed on the second surface;
(c) covering the semiconductor chip in a resin sealing body, wherein the step (b) includes the steps of:
(b1) mounting the semiconductor chip in a region enclosed by the upper part and the side part of the conductive cap via a connection material for cap between the upper electrode of the semiconductor chip and the upper part of the conductive cap;
(b2) mounting first and second, external connection terminals on the first and the second lower electrodes of the semiconductor chip via first and second connection materials respectively; and
(b3) heating and melting the connection material for cap, the first connection material and the second connection material so that the upper electrode of the semiconductor chip is bonded to the upper part of the conductive cap via the connection material for cap, the first lower-electrode of the semiconductor chip is bonded to the first external connection terminal via the first connection material, and the second lower electrode of the semiconductor chip is bonded to the second external connection terminal via the second connection material, and
wherein the step (c) includes the steps of:
(c1) filling the resin sealing body into the region enclosed by the upper part and the side part of the conductive cap so that the semiconductor chip is covered and the first and the second, external connection terminals are exposed, and
(c2) heating and curing the resin sealing body.
23 . The method for manufacturing the semiconductor device according to claim 22 , wherein in the step (b3), a mounting-board opposing surface of the leg of the conductive cap, and mounting-board opposing surfaces of the first and the second, external connection terminals are disposed in the same plane.
24 . The method for manufacturing the semiconductor device according to claim 22 , wherein the first and the second, external connection terminals have a function of loosening control of a surface level of the resin sealing body during filling the resin sealing body in the step (c1).
25 . The method for manufacturing the semiconductor device according to claim 22 , wherein the first and the second, external connection terminals have a function of making an outer terminal of the semiconductor device to be versatile.
26 . The method for manufacturing the semiconductor device according to claim 22 , wherein the first external connection terminal, the second external connection terminal, the first connection material, and the second connection material have a function of buffering thermal stress generated due to difference in thermal expansion coefficient between the semiconductor chip and the mounting board.Join the waitlist — get patent alerts
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