Chip-Stacked Package Structure and Applications Thereof

Abstract

A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, circuit board and a second chip. The substrate has a first surface and an opposite second surface. The first chip having a first active surface and an opposite first rear surface is electrically connected to first surface of substrate serving by a flip chip bonding process. The circuit board has a dielectric layer set on the first rear surface and a patterned conductive layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned conductive layer has a plurality of second pads formed on a second active surface thereof and eclectically connected to the patterned conductive layer.

1 . A chip-stacked package structure, comprising:
 a substrate having a first surface and a second surface opposite to the first surface;   a first chip set on the first surface of the substrate, having a first active surface, a first rear surface, and at least one first bonding pad, wherein the first active surface faces to the substrate, and the first bonding pad is electrically connected to the substrate;   a circuit board set on the first rear surface comprising:
 a dielectric layer set on the first rear surface; and 
 a patterned circuit layer formed on the dielectric layer and electrically connected to the substrate via at least one bonding wire; 
   a second chip set on the patterned circuit layer having a second active surface and at least one second bonding pad set on the second active surface, and the second bonding pad is electrically connected to the patterned circuit layer, and electrically connected to the substrate via the bonding wire; and   a molding compound encapsulates the first chip, the substrate, the circuit board and the second chip.   
     
     
         2 . The chip-stacked package structure in accordance with  claim 1 , further comprising a plurality of external connecting bumps set on the second surface of the substrate. 
     
     
         3 . The chip-stacked package structure in accordance with  claim 1 , wherein the first active surface has a plurality of first bonding pads electrically connected to the substrate via a plurality of bumps. 
     
     
         4 . The chip-stacked package structure in accordance with  claim 2 , further comprising underfill materials used to encapsulate the bumps. 
     
     
         5 . The chip-stacked package structure in accordance with  claim 2 , wherein the substrate has a through hole used to expose a portion of the first active surface. 
     
     
         6 . The chip-stacked package structure in accordance with  claim 5 , wherein the first active surface has a plurality of first bonding pads electrically connected to the substrate via a plurality of bumps. 
     
     
         7 . The chip-stacked package structure in accordance with  claim 6 , further comprising underfill materials used to encapsulate the bumps. 
     
     
         8 . The chip-stacked package structure in accordance with  claim 7 , further comprising a heat sink extending outward the through hole form the exposed portion of the first active surface. 
     
     
         9 . The chip-stacked package structure in accordance with  claim 5 , wherein the first active surface has a plurality of first bonding pads set thereon and electrically connected to the substrate via a plurality of bonding wires passing through the through hole. 
     
     
         10 . The chip-stacked package structure in accordance with  claim 1 , wherein the patterned circuit layer is a redistribution layer. 
     
     
         11 . The chip-stacked package structure in accordance with  claim 1 , wherein the patterned circuit layer comprises a plurality of fingers, and one end of each finger is used to electrically connect to one of the second bonding pad, and the other end of the corresponding finger extends towards the edge of the first rear surface. 
     
     
         12 . The chip-stacked package structure in accordance with  claim 1 , wherein the first rear surface and the second active surface have an identical size. 
     
     
         13 . The chip-stacked package structure in accordance with  claim 1 , wherein the first rear surface and the second active surface have different size. 
     
     
         14 . The chip-stacked package structure in accordance with  claim 1 , wherein the second bonding pad is electrically connected to the patterned circuit layer by at least one bump or by at lest one solder. 
     
     
         15 . A method for manufacturing a chip-stacked package structure, comprising:
 providing a substrate that has a first surface and a second surface opposite to the first surface;   setting a first chip on the first surface of the substrate, to make a first active surface of the first chip that facing and electrically connecting to the substantiate;   forming a circuit board set on a first rear surface of the first chip opposite to the first active surface, wherein the circuit board comprises a dielectric layer set on the first rear surface and a patterned circuit layer formed on the dielectric layer, and the patterned circuit layer has at least one finger electrically connected to at least one second bonding pad set on a second chip that is subsequently stacked thereon;   forming at least one bonding wire to electrically connect the patterned circuit layer with the substrate;   setting the second chip on the patterned circuit layer to make the second bonding pad electrically connected to the finger and electrically connected to the substrate via the bonding wire; and   using a molding compound to encapsulates the first chip, the substrate, the circuit board and the second chip.   
     
     
         16 . The method for manufacturing the chip-stacked package structure in accordance with  claim 15 , wherein the step of providing the substrate further comprises a step of providing a plurality of external connecting bumps set on the second surface of the substrate. 
     
     
         17 . The method for manufacturing the chip-stacked package structure in accordance with  claim 16 , wherein the step of setting a first chip on the first surface of the substrate comprises steps as follows:
 forming a plurality of bumps on the first active surface electrically connected to the substrate; and   using underfill materials to encapsulate the bumps.   
     
     
         18 . The method for manufacturing the chip-stacked package structure in accordance with  claim 15 , wherein the step of providing the substrate further comprises a step of forming a though hole penetrating through the substrate to expose a portion of the first active surface. 
     
     
         19 . The method for manufacturing the chip-stacked package structure in accordance with  claim 18 , wherein the step of setting a first chip on the first surface of the substrate comprises steps as follows:
 forming a plurality of bumps on the first active surface electrically connected to the substrate; and   using underfill materials to encapsulate the bumps.   
     
     
         20 . The method for manufacturing the chip-stacked package structure in accordance with  claim 19 , further comprising setting a heat sink extending outward the through hole from the exposed portion of the first active surface. 
     
     
         21 . The method for manufacturing the chip-stacked package structure in accordance with  claim 18 , wherein the step of setting a first chip on the first surface of the substrate comprises steps as follows:
 setting the first chip on the substrate to expose a plurality of first bonding pads that are set on the first active surface via the through hole; and   forming at least one bonding wire passing though the though hole to electrically connect the first bonding pads with the substrate.