Structure and method for enhanced triple well latchup robustness

Abstract

Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p-substrate but also beneath the n-well. The structure eliminates the spacing issues between the n-well and n+ buried layer by extending the n+ buried layer below the entire device. The structure also addresses the issue of threshold voltage scattering by providing a p+ buried layer below the entire device under the n+ buried layer or below the p-well side of the device only either under or above the n+ buried layer) Latchup robustness can further be improved by incorporating into the device an isolation structure that eliminates lateral pnp, npn, or pnpn devices and/or a sub-collector region between the n+ buried layer and the n-well.

1 . A complementary metal oxide semiconductor device comprising:
 a substrate with a first conductivity type;   a first semiconductor layer with said first conductivity type above said substrate;   a second semiconductor layer with a second conductivity type above said first semiconductor layer; and   a first semiconductor well with said second conductivity type adjacent to a second semiconductor well with said first conductivity type,   wherein said second semiconductor layer extends laterally below said first semiconductor well so as to degrade vertical bipolar current gain and below said second semiconductor well so as to isolate said second semiconductor well from said substrate and   wherein said first semiconductor layer extends laterally below both said first semiconductor well and said second semiconductor well.   
   
   
       2 . The device of  claim 1 , wherein said first semiconductor layer has first outer edges, wherein said second semiconductor layer has second outer edges, and wherein said first outer edges are aligned directly below said second outer edges. 
   
   
       3 . The device of  claim 1 , wherein said second semiconductor layer comprises second outer edges and wherein said first semiconductor layer extends laterally beyond said second outer edges. 
   
   
       4 . The device of  claim 1 , further comprising an isolation structure that extends from a top surface of said device to below an upper surface of said second semiconductor layer. 
   
   
       5 . The device of  claim 4 , wherein said isolation structure further extends into said substrate. 
   
   
       6 . The device of  claim 4 , wherein said isolation structure bifurcates said first semiconductor well. 
   
   
       7 . The device of  claim 4 , wherein said isolation structure separates said first semiconductor well and said second semiconductor well and wherein a portion of said second semiconductor layer below said second semiconductor well abuts said isolation structure. 
   
   
       8 . The device of  claim 1 , further comprising a sub-collector region with said second conductivity type between said first semiconductor well and said second semiconductor layer. 
   
   
       9 . A complementary metal oxide semiconductor device comprising:
 a substrate with a first conductivity type;   a first semiconductor layer with said first conductivity type above said substrate;   a second semiconductor layer with a second conductivity type above said first semiconductor layer; and   a first semiconductor well with said second conductivity type adjacent to a second semiconductor well with said first conductivity type,   wherein said second semiconductor layer extends laterally below said first semiconductor well so as to degrade vertical bipolar current gain and below said second semiconductor well so as to isolate said second semiconductor well from said substrate and   wherein said second semiconductor well and not said first semiconductor well is above said first semiconductor layer.   
   
   
       10 . The device of  claim 9 , further comprising an isolation structure that extends from a top surface of said device to below an upper surface of said second semiconductor layer. 
   
   
       11 . The device of  claim 10 , wherein said isolation structure bifurcates said first semiconductor well. 
   
   
       12 . The device of  claim 10 , wherein said isolation structure separates said first semiconductor well and said second semiconductor well and wherein a portion of said second semiconductor layer below said second semiconductor well abuts said second isolation structure. 
   
   
       13 . The device of  claim 9 , further comprising a sub-collector region with said second conductivity type between said first semiconductor well and said second semiconductor layer. 
   
   
       14 . A complementary metal oxide semiconductor device comprising:
 a substrate with a first conductivity type;   a first semiconductor layer with said first conductivity type above said substrate;   a second semiconductor layer with a second conductivity type above said first semiconductor layer; and   a first semiconductor well with said second conductivity type adjacent to a second semiconductor well with said first conductivity type,   wherein said second semiconductor layer extends laterally below said first semiconductor well so as to degrade vertical bipolar current gain and below said second semiconductor well so as to isolate said second semiconductor well from said substrate, and   wherein said second semiconductor well and not said first semiconductor well is above said first semiconductor layer;   an isolation structure that extends from a top surface of said device to below an upper surface of said second semiconductor layer.   
   
   
       15 . The device of  claim 14 , wherein said isolation structure bifurcates said first semiconductor well. 
   
   
       16 . The device of  claim 14 , wherein said isolation structure separates said first semiconductor well and said second semiconductor well and wherein a portion of said second semiconductor layer below said second semiconductor well abuts said second isolation structure. 
   
   
       17 . The device of  claim 14 , further comprising a sub-collector region with said second conductivity type between said first semiconductor well and said second semiconductor layer.