Semiconductor device manufacturing method including forming a metal silicide layer on an indium-containing layer

Abstract

The present invention provides a semiconductor device manufacturing method of a semiconductor device having a contact plug, in which a contact hole formed by a surface portion of a high-concentration N-type diffusion layer formed on a semiconductor silicon substrate surface and an interlayer insulating film is implanted with indium ions at an energy ranging from 30 to 120 keV and an implantation amount ranging from 1.0×10 13 /cm 2 to 5.0×10 14 /cm 2 to grow an indium-containing layer on the surface portion of the high-concentration N-type diffusion layer at the bottom of the contact hole.

1 - 9 . (canceled) 
   
   
       10 . A semiconductor device comprising:
 a semiconductor silicon substrate;   a high-concentration N-type diffusion layer provided on a surface of said semiconductor silicon substrate;   an indium-containing layer provided in said high-concentration N-type diffusion layer;   an interlayer insulating film provided at a predetermined position on said semiconductor silicon substrate;   a barrier layer provided in contact with an inner surface of a contact hole defined by the surface of said semiconductor silicon substrate and said interlayer insulating film and with said interlayer insulating film;   a contact plug provided in contact with said barrier layer; and   a metal silicide layer provided at a boundary region between said indium-containing layer and said barrier layer,   wherein indium concentration of said indium-containing layer ranges from 5.0×10 18 /cm 3  to 5.0×10 19 /cm 3 .   
   
   
       11 . The semiconductor device according to  claim 10 , comprising an N channel insulated gate field effect transistor structure. 
   
   
       12 . The semiconductor device according to  claim 10 , comprising an N channel insulated gate field effect transistor structure. 
   
   
       13 . The semiconductor device according to  claim 10 , wherein the metal silicide layer has a thickness of about 10 nm, the indium-containing layer has a depth of 25 nm or more from the surface of the semiconductor substrate, and the high-concentration N-type diffusion layer has a depth of 100 to 150 nm from the surface of the semiconductor substrate. 
   
   
       14 . A semiconductor device comprising:
 a semiconductor silicon substrate;   a high-concentration N-type diffusion layer provided on a surface of said semiconductor silicon substrate;   an indium-containing layer provided in said high-concentration N-type diffusion layer;   an interlayer insulating film provided at a predetermined position on said semiconductor silicon substrate;   a barrier layer provided in contact with an inner surface of a contact hole defined by the surface of said semiconductor silicon substrate and said interlayer insulating film and with said interlayer insulating film;   a contact plug provided in contact with said barrier layer; and   a metal silicide layer provided at a boundary region between said indium-containing layer and said barrier layer,   wherein the metal silicide layer has a thickness of about 10 nm, the indium-containing layer has a depth of 25 nm or more from the surface of the semiconductor substrate, and the high-concentration N-type diffusion layer has a depth of 100 to 150 nm from the surface of the semiconductor substrate.   
   
   
       15 . The semiconductor device according to  claim 14 , comprising an N channel insulated gate field effect transistor structure. 
   
   
       16 . The semiconductor device according to  claim 10 , comprising an N channel insulated gate field effect transistor structure. 
   
   
       17 . A semiconductor device having an N-channel insulated gate transistor, the transistor comprising N-type source and N-type drain regions selectively formed in P-type region to define a channel region therebetween, an insulated gate structure covering the channel region, and source and drain electrodes formed in contact respectively with the N-type source and N-type drain regions, at least one of the N-type source and N-type drain regions including a first portion which represents the N-type and which contains indium and a second portion which represents the N-type and which contains substantially no indium, the first portion being surrounded by the second portion and in contact with a corresponding one of the source and drain electrodes. 
   
   
       18 . The device as claimed in  claim 17 , wherein each of the first and second portions is doped with N-type impurities at a high concentration to represent the N-type. 
   
   
       19 . The device as claimed in  claim 17 , wherein the first portion contains indium at a concentration of 5.0×10 18 /cm 3  to 5.0×10 19 /cm 3 . 
   
   
       20 . The device as claimed in  claim 17 , further comprising an insulating layer covering the transistor and a contact hole selectively formed in the insulating layer to expose a part of the first portion, the corresponding one of the source and drain electrodes including a metal silicide layer formed in contact with the part of the first portion and a contact plug filling the contact hole in contact with the metal silicide layer. 
   
   
       21 . The device as claimed in  claim 20 , wherein the contact plug includes a conductive layer and a barrier metal layer sandwiched between the conductive layer and the metal silicide layer. 
   
   
       22 . The device as claimed in  claim 21 , wherein the first portion contains indium at a concentration of 5.0×10 18 /cm 3  to 5.0×10 19 /cm 3 .