Dynamic core switching

Abstract

A system includes a first asymmetric core, a second asymmetric core, and a core switching module. The first asymmetric core executes an application when the system operates in a first mode and is inactive when the system operates in a second mode. The second asymmetric core executes the application when the system operates in the second mode. The core switching module switches operation of the system between the first mode and the second mode. The core switching module selectively stops processing of the application by the first asymmetric core after receiving a first control signal. The core switching module transfers a first state of the first asymmetric core to the second asymmetric core. The second asymmetric core resumes executing the application in the second mode.

1 . A system comprising:
 a first asymmetric core that executes an application when said system operates in a first mode and that is inactive when said system operates in a second mode;   a second asymmetric core that executes said application when said system operates in said second mode; and   a core switching module that switches operation of said system between said first mode and said second mode, that selectively stops processing of said application by said first asymmetric core after receiving a first control signal, and that transfers a first state of said first asymmetric core to said second asymmetric core, wherein said second asymmetric core resumes executing said application in said second mode.   
     
     
         2 . The system of  claim 1  wherein said first control signal indicates that interrupts are disabled. 
     
     
         3 . The system of  claim 1  wherein instructions are executed without instruction translation when said second asymmetric core resumes executing said application during said second mode. 
     
     
         4 . The system of  claim 1  further comprising an operating system (OS) that provides services to said application, wherein said core switching module switches execution of said application between said first asymmetric core and said second asymmetric core transparently to said OS. 
     
     
         5 . The system of  claim 1  wherein a first maximum speed of said first asymmetric core is greater than a second maximum speed of said second asymmetric core. 
     
     
         6 . The system of  claim 1  wherein said first asymmetric core operates at frequencies greater than a predetermined frequency, and wherein said second asymmetric core operates at frequencies less than said predetermined frequency. 
     
     
         7 . The system of  claim 1  wherein a first maximum operating power level of said first asymmetric core is greater than a second maximum operating power level of said second asymmetric core. 
     
     
         8 . The system of  claim 1  wherein said first asymmetric core uses a first instruction set architecture (ISA) and said second asymmetric core uses a second ISA, and wherein said first ISA is compatible with said second ISA. 
     
     
         9 . The system of  claim 8  wherein a first set of instructions of said first ISA is a superset of a second set of instructions of said second ISA, and wherein said first set includes more instructions than said second set. 
     
     
         10 . The system of  claim 4  wherein said OS comprises a kernel, and wherein said core switching module executes above a level of said kernel. 
     
     
         11 . The system of  claim 1  further comprising a hypervisor module, wherein said core switching module is integrated with said hypervisor module. 
     
     
         12 . The system of  claim 1  wherein said core switching module saves said first state when said core switching module selectively stops processing of said application by said first asymmetric core. 
     
     
         13 . The system of  claim 12  wherein said core switching module powers up said second asymmetric core and initializes said second asymmetric core using said first state. 
     
     
         14 . The system of  claim 2  wherein said interrupts are enabled after said second asymmetric core resumes executing said application. 
     
     
         15 . The system of  claim 13  wherein said core switching module shuts down said first asymmetric core when said second asymmetric core powers up, and wherein one of no power and standby power is supplied to said first asymmetric core after said first asymmetric core is shut down. 
     
     
         16 . The system of  claim 15  further comprising a level-2 (L2) cache that communicates with said first asymmetric core, wherein one of no power and standby power is supplied to said L2 cache after said first asymmetric core is shut down. 
     
     
         17 . The system of  claim 13  wherein said core switching module initializes said first asymmetric core using said first state when said second asymmetric core fails to power up, wherein said first asymmetric core resumes executing said application in said first mode, and wherein interrupts are enabled. 
     
     
         18 . The system of  claim 1  wherein said core switching module switches operation of said system between said second mode and said first mode, selectively stops processing of said application by said second asymmetric core after receiving said first control signal, and transfers a second state of said second asymmetric core to said first asymmetric core, wherein said first asymmetric core resumes executing said application in said first mode, and wherein said first control signal indicates that interrupts are disabled. 
     
     
         19 . The system of  claim 18  wherein instructions are executed without instruction translation when said first asymmetric core resumes executing said application during said first mode. 
     
     
         20 . The system of  claim 18  further comprising an operating system (OS) that provides services to said application, wherein said core switching module switches execution of said application between said second asymmetric core and said first asymmetric core transparently to said OS. 
     
     
         21 . The system of  claim 18  wherein said core switching module saves said second state when said core switching module selectively stops processing of said application by said second asymmetric core. 
     
     
         22 . The system of  claim 21  wherein said core switching module powers up said first asymmetric core and initializes said first asymmetric core using said second state. 
     
     
         23 . The system of  claim 18  wherein said interrupts are enabled after said first asymmetric core resumes executing said application. 
     
     
         24 . The system of  claim 22  further comprising a level-2 (L2) cache that communicates with said first asymmetric core, wherein power is supplied to said L2 cache after said first asymmetric core powers up. 
     
     
         25 . The system of  claim 22  wherein said core switching module shuts down said second asymmetric core when said first asymmetric core powers up, and wherein one of no power and standby power is supplied to said second asymmetric core after said second asymmetric core is shut down. 
     
     
         26 . The system of  claim 22  wherein said core switching module initializes said second asymmetric core using said second state when said first asymmetric core fails to power up, and wherein said second asymmetric core resumes executing said application in said second mode, and wherein said interrupts are enabled. 
     
     
         27 . The system of  claim 1  further comprising a core profile module that generates a second control signal based on at least one of core utilization, resource utilization, and performance of said application. 
     
     
         28 . The system of  claim 27  further comprising a core change sequence (CCS) module that initiates a CCS based on said second control signal, wherein said core switching module switches execution of said application between one of said first and second asymmetric cores and another of said first and second asymmetric cores based on said CCS. 
     
     
         29 . The system of  claim 28  wherein said CCS module initiates said CCS when at least one of:
 said core utilization of said second asymmetric core by said application is greater than or equal to a first predetermined threshold;   said core utilization of said second asymmetric core by said application is greater than or equal to a second predetermined threshold for a first predetermined time period;   an anticipated core utilization of said second asymmetric core is greater than or equal to a third predetermined threshold, wherein said anticipated core utilization is determined based on at least one of a type of said application and a history of execution of said application;   said core utilization of said first asymmetric core by said application is less than or equal to a fourth predetermined threshold; and   said core utilization of said first asymmetric core by said application is less than or equal to a fifth predetermined threshold for a second predetermined time period.   
     
     
         30 . The system of  claim 28  wherein said CCS module initiates said CCS based on at least one of a type of said application, a number of applications, and a type of instruction. 
     
     
         31 . The system of  claim 27  wherein said core profile module generates said second control signal based on a number of times execution of applications is switched between one of said first and second asymmetric cores and another of said first and second asymmetric cores. 
     
     
         32 . The system of  claim 27  further comprising a power control module that controls power consumption of said system and that generates a third control signal based on said second control signal and said power consumption. 
     
     
         33 . The system of  claim 32  further comprising a core change sequence (CCS) module that initiates a CCS based on said third control signal, wherein said core switching module switches execution of said application between one of said first and second asymmetric cores and another of said first and second asymmetric cores based on said CCS. 
     
     
         34 . The system of  claim 28  further comprising a frequency change sequence (FCS) module that initiates a FCS based on said second control signal and that selects an operating frequency of at least one of said first and second asymmetric cores based on said FCS. 
     
     
         35 . The system of  claim 28  further comprising a voltage change sequence (VCS) module that initiates a VCS based on said second control signal and that selects a supply voltage of at least one of said first and second asymmetric cores based on said VCS. 
     
     
         36 . The system of  claim 18  further comprising a power management module that disables said interrupts when said system switches said operation between said first mode and said second mode and that disables said interrupts when said system switches said operation between said second mode and said first mode. 
     
     
         37 . The system of  claim 28  further comprising a plurality of said first asymmetric core, wherein said core switching module selectively activates and deactivates more than one of said plurality of said first asymmetric core based on said CCS when said system operates in said first mode. 
     
     
         38 . The system of  claim 1  further comprising a glue logic module that selectively communicates with said core switching module and that:
 receives interrupts;   receives first signals from said application; and   routes said interrupts and said first signals to said one of said first and second asymmetric cores activated by said core switching module.   
     
     
         39 . A system-on-chip (SOC) comprising the system of  claim 1 . 
     
     
         40 . A system-in-package (SIP) comprising the system of  claim 1 . 
     
     
         41 . A method comprising:
 executing an application using a first asymmetric core when operating in a first mode, wherein said first asymmetric core is inactive when operating in a second mode;   switching operation between said first mode and said second mode using a core switching module;   selectively stopping processing of said application by said first asymmetric core using said core switching module after receiving a first control signal;   transferring a first state of said first asymmetric core to said second asymmetric core using said core switching module; and   resuming execution of said application in said second mode using said second asymmetric core.   
     
     
         42 . The method of  claim 41  further comprising disabling interrupts and indicating via said first control signal that said interrupts are disabled. 
     
     
         43 . The method of  claim 41  further comprising executing instructions without instruction translation when said second asymmetric core resumes executing said application during said second mode. 
     
     
         44 . The method of  claim 41  further comprising:
 providing services to said application via an operating system (OS); and   switching execution of said application between said first asymmetric core and said second asymmetric core transparently to said OS using said core switching module.   
     
     
         45 . The method of  claim 41  further comprising:
 selectively operating said first asymmetric core at a first maximum speed; and   selectively operating said second asymmetric core at a second maximum speed,   wherein said first maximum speed is greater than said second maximum speed.   
     
     
         46 . The method of  claim 41  further comprising:
 selectively operating said first asymmetric core at a first maximum operating power level; and   selectively operating said second asymmetric core at a second maximum operating power level,   wherein said first maximum operating power level is greater than said second maximum operating power level.   
     
     
         47 . The method of  claim 41  further comprising:
 selectively operating said first asymmetric core at frequencies greater than a predetermined frequency; and   selectively operating said second asymmetric core at frequencies less than said predetermined frequency.   
     
     
         48 . The method of  claim 41  further comprising:
 operating said first asymmetric core using a first instruction set architecture (ISA); and   operating said second asymmetric core using a second ISA,   wherein said first ISA is compatible with said second ISA.   
     
     
         49 . The method of  claim 48  further comprising:
 operating said first asymmetric core using a first set of instructions of said first ISA; and   operating said second asymmetric core using a second set of instructions of said second ISA,   wherein said first set is a superset of said second set, and wherein said first set includes more instructions than said second set.   
     
     
         50 . The method of  claim 44  further comprising:
 providing a kernel of said OS; and   executing said core switching module above a level of said kernel.   
     
     
         51 . The method of  claim 41  further comprising:
 providing a hypervisor module; and   integrating said core switching module with said hypervisor module.   
     
     
         52 . The method of  claim 41  further comprising saving said first state when said core switching module selective stops processing of said application by said first asymmetric core. 
     
     
         53 . The method of  claim 52  further comprising:
 powering up said second asymmetric core; and   initializing said second asymmetric core using said first state.   
     
     
         54 . The method of  claim 42  further comprising enabling said interrupts after said second asymmetric core resumes executing said application. 
     
     
         55 . The method of  claim 53  further comprising:
 shutting down said first asymmetric core when said second asymmetric core powers up; and   supplying one of no power and standby power to said first asymmetric core after said first asymmetric core is shut down.   
     
     
         56 . The method of  claim 55  further comprising:
 providing a level-2 (L2) cache, wherein said first asymmetric core communicates with said L2 cache when said first asymmetric core is active; and   supplying one of no power and standby power to said L2 cache after said first asymmetric core is shut down.   
     
     
         57 . The method of  claim 53  further comprising:
 initializing said first asymmetric core using said first state when said second asymmetric core fails to power up;   resuming execution of said application in said first mode using said first asymmetric core; and   enabling interrupts.   
     
     
         58 . The method of  claim 41  further comprising:
 switching operation between said second mode and said first mode using a core switching module;   selectively stopping processing of said application by said second asymmetric core using said core switching module after receiving said first control signal indicating that interrupts are disabled;   transferring a second state of said second asymmetric core to said first asymmetric core using said core switching module; and   resuming execution of said application in said first mode using said first asymmetric core.   
     
     
         59 . The method of  claim 58  further comprising executing instructions without instruction translation when said first asymmetric core resumes executing said application during said first mode. 
     
     
         60 . The method of  claim 58  further comprising:
 providing services to said application via an operating system (OS); and   switching execution of said application between said second asymmetric core and said first asymmetric core transparently to said OS using said core switching module.   
     
     
         61 . The method of  claim 58  further comprising saving said second state when said core switching module selective stops processing of said application by said second asymmetric core. 
     
     
         62 . The method of  claim 61  further comprising:
 powering up said first asymmetric core; and   initializing said first asymmetric core using said second state.   
     
     
         63 . The method of  claim 58  further comprising enabling said interrupts after said first asymmetric core resumes executing said application. 
     
     
         64 . The method of  claim 62  further comprising:
 providing a level-2 (L2) cache, wherein said first asymmetric core communicates with said L2 cache when said first asymmetric core is active; and   supplying power to said L2 cache after said first asymmetric core powers up.   
     
     
         65 . The method of  claim 62  further comprising:
 shutting down said second asymmetric core when said first asymmetric core powers up; and   supplying one of no power and standby power to said second asymmetric core after said second asymmetric core is shut down.   
     
     
         66 . The method of  claim 62  further comprising:
 initializing said second asymmetric core using said second state when said first asymmetric core fails to power up;   resuming execution of said application in said second mode using said second asymmetric core; and   enabling said interrupts.   
     
     
         67 . The method of  claim 41  further comprising generating a second control signal based on at least one of core utilization, resource utilization, and performance of said application. 
     
     
         68 . The method of  claim 67  further comprising:
 initiating a core change sequence (CCS) based on said second control signal; and   switching execution of said application between one of said first and second asymmetric cores and another of said first and second asymmetric cores based on said CCS using said core switching module.   
     
     
         69 . The method of  claim 68  further comprising initiating said CCS when at least one of:
 said core utilization of said second asymmetric core by said application is greater than or equal to a first predetermined threshold;   said core utilization of said second asymmetric core by said application is greater than or equal to a second predetermined threshold for a first predetermined time period;   said core utilization of said first asymmetric core by said application is less than or equal to a third predetermined threshold; and   said core utilization of said first asymmetric core by said application is less than or equal to a fourth predetermined threshold for a second predetermined time period.   
     
     
         70 . The method of  claim 68  further comprising:
 determining an anticipated core utilization based on at least one of a type of said application and a history of execution of said application; and   initiating said CCS when said anticipated core utilization of said second asymmetric core is greater than or equal to a predetermined threshold.   
     
     
         71 . The method of  claim 68  further comprising initiating said CCS based on at least one of:
 a number of applications executed by one of said first and second asymmetric cores;   a type of said application executed by one of said first and second asymmetric cores; and   a type of instruction executed by one of said first and second asymmetric cores.   
     
     
         72 . The method of  claim 67  further comprising generating said second control signal based on a number of times execution of applications is switched between one of said first and second asymmetric cores and another of said first and second asymmetric cores. 
     
     
         73 . The method of  claim 67  further comprising:
 controlling power consumption;   generating a third control signal based on said second control signal and said power consumption;   initiating a core change sequence (CCS) based on said third control signal; and   switching execution of said application between one of said first and second asymmetric cores and another of said first and second asymmetric cores based on said CCS using said core switching module.   
     
     
         74 . The method of  claim 68  further comprising:
 initiating a frequency change sequence (FCS) based on said second control signal; and   selecting an operating frequency of at least one of said first and second asymmetric cores based on said FCS.   
     
     
         75 . The method of  claim 68  further comprising:
 initiating a voltage change sequence (VCS) based on said second control signal; and   selecting a supply voltage of at least one of said first and second asymmetric cores based on said VCS.   
     
     
         76 . The method of  claim 68  further comprising:
 providing a plurality of said first asymmetric core; and   selectively activating and deactivating more than one of said plurality of said first asymmetric core based on said CCS when operating in said first mode using said core switching module.   
     
     
         77 . The method of  claim 41  further comprising:
 providing a glue logic module;   selectively communicating with said core switching module using said glue logic module;   receiving interrupts via said glue logic module;   receiving first signals from said application via said glue logic module; and   routing said interrupts and said first signals to said one of said first and second asymmetric cores activated by said core switching module using said glue logic module.   
     
     
         78 . The method of  claim 41  further comprising providing said first and second asymmetric cores and said core switching module in one of a system-on-chip (SOC) and a system-in-package (SIP).