Single-chip microcomputer

Abstract

A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

1 - 16 . (canceled) 
     
     
         17 . A data processor comprising:
 a central processing unit;   an internal memory accessed by said central processing unit;   an external interface unit coupled to an external memory, and providing control signals and an address signal synchronized with a clock signal to said external memory; and   a data transfer controller operable to transfer data between said internal memory and said external memory,   wherein said central processing unit is operable to access said external memory, and   wherein said data processor is operable to provide said clock signal to said external memory.   
     
     
         18 . A data processor according to  claim 17 ,
 wherein said control signals include a RAS signal and a CAS signal.   
     
     
         19 . A data processor according to  claim 18 ,
 wherein said internal memory is a cache memory coupled to said central processing unit.   
     
     
         20 . A data processor according to  claim 17 ,
 wherein said central processing unit is coupled to said internal memory via an internal bus.   
     
     
         21 . A data processor according to  claim 20 ,
 wherein said data processor further includes a peripheral module,   wherein said data transfer controller is operable to transfer data between said peripheral module and said external memory.   
     
     
         22 . A data processing unit, comprising:
 a CPU;   an internal memory;   a memory controller coupled to an external memory, and providing a RAS signal, a CAS signal, an address signal and a clock signal to said external memory; and   a data transfer controller transferring data between said internal memory and said external memory,   wherein said CPU is operable to access said external memory,   wherein said internal memory is operable to store an instruction executed by said CPU, and   wherein said memory controller provides said RAS signal, CAS signal and address signal synchronized with said clock signal.   
     
     
         23 . A data processing unit according to  claim 22 ,
 wherein said internal memory is cache memory.   
     
     
         24 . A data processing unit according to  claim 23 ,
 wherein said data processor is operable to set an operation mode of said external memory.