Semiconductor Devices Including an Amorphous Region in an Interface Between a Device Isolation Layer and a Source/Drain Diffusion Layer

Abstract

Semiconductor devices and methods for fabricating the same are disclosed in which an amorphous layer is formed in an interface between a device isolation layer and a source or drain region to stably thin a silicide layer formed in the interface. A leakage current of the silicide layer formed in the interface between the device isolation layer and the source/drain region is reduced.

1 . A semiconductor device comprising:
 a semiconductor substrate including an active region and a field region;   a device isolation layer in the field region;   a gate electrode on the active region;   source/drain regions on opposite sides of the gate electrode; and   an amorphous layer in at least one of the source region and the drain region, adjacent to the device isolation layer.   
   
   
       2 . The semiconductor device of  claim 1 , wherein the amorphous layer has a thickness between about 1 μm and about 5 μm. 
   
   
       3 . The semiconductor device of  claim 1 , further comprising a silicide layer on the surface of the source/drain regions, including on the amorphous layer. 
   
   
       4 . The semiconductor device of  claim 1 , further comprising sidewall insulating layers on opposite sidewalls of the gate electrode. 
   
   
       5 . The semiconductor device of  claim 1 , wherein the amorphous layer is at interfaces between the device isolation layer and the source/drain regions. 
   
   
       6 . The semiconductor device of  claim 1 , wherein the silicide layer comprises Si X W Y  or SiTi X . 
   
   
       7 . The semiconductor device of  claim 1 , wherein the gate electrode comprises silicon. 
   
   
       8 . The semiconductor device of  claim 7 , wherein the silicide layer is on the surface of the gate electrode. 
   
   
       9 . The semiconductor device of  claim 1 , wherein the amorphous layer comprises Ge +  ions. 
   
   
       10 . The semiconductor device of  claim 3 , wherein the silicide layer comprises a refractory metal silicide. 
   
   
       11 . The semiconductor device of  claim 1 , further comprising an insulating layer on the gate and the source/drain regions. 
   
   
       12 . The semiconductor device of  claim 11 , further comprising a contact hole in the insulating layer. 
   
   
       13 . The semiconductor device of  claim 12 , further comprising a metal line on the insulating layer. 
   
   
       14 . The semiconductor device of  claim 1 , wherein the device isolation layer comprises a planarized LOCOS or STI layer. 
   
   
       15 . The semiconductor device of  claim 4 , wherein the sidewall insulating layers comprise an oxide or a nitride. 
   
   
       16 . The semiconductor device of  claim 1 , further comprising a gate insulating layer over the substrate and below the gate electrode. 
   
   
       17 . The semiconductor device of  claim 1 , further comprising a uniform silicide layer at interfaces between the device isolation layer and the amorphous layers.