US2008257742A1PendingUtilityA1
Method of manufacturing printed circuit board for semiconductor package
Est. expiryApr 18, 2027(~0.7 yrs left)· nominal 20-yr term from priority
H10W 70/687H10W 70/05H05K 3/244H05K 2203/0723H05K 2203/072H05K 2201/0391H05K 3/243H05K 3/18
40
PatentIndex Score
0
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Claims
Abstract
Disclosed is a method of manufacturing a printed circuit board for a semiconductor package, which minimizes or completely obviates masking work upon the plating of each pad for the surface treatment of a printed circuit board for a semiconductor package, thereby simplifying the overall process and increasing the mounting reliability.
Claims
exact text as granted — not AI-modified1 . A method of manufacturing a printed circuit board for a semiconductor package, comprising:
(a) providing a printed circuit board for a package, including wire bonding pads and surface mount device mounting pads and having a predetermined circuit pattern; (b) forming a solder resist layer on a portion of the printed circuit board, other than the wire bonding pads and the surface mount device mounting pads; (c) forming an electroless nickel immersion gold layer, composed of an electroless nickel plating layer and an electroless gold plating layer, on each of the wire bonding pads and surface mount device mounting pads, through electroless nickel plating and electroless gold plating; and (d) forming a gold electroplating layer on the electroless nickel immersion gold layer of the surface mount device mounting pad to which a plating lead wire is connected, among the surface mount device mounting pads, and the electroless nickel immersion gold layer of each of the wire bonding pads, through gold electroplating.
2 . The method as set forth in claim 1 , wherein the electroless gold plating layer of the electroless nickel immersion gold layer has a thickness ranging from 0.01 μm to 0.1 μm.
3 . The method as set forth in claim 1 , wherein the electroless nickel plating layer of the electroless nickel immersion gold layer has a thickness ranging from 0.3 μm to 15 μm.
4 . The method as set forth in claim 1 , wherein the gold electroplating layer has a thickness ranging from 0.1 μm to 1.0 μm.
5 . A method of manufacturing a printed circuit board for a semiconductor package, comprising:
(a) providing a printed circuit board for a package, including wire bonding pads, surface mount device mounting pads and ZIF connector pads and having a predetermined circuit pattern; (b) forming a solder resist layer on a portion of the printed circuit board, other than the wire bonding pads, the surface mount device mounting pads, and the ZIF connector pad; (c) applying a plating resist on a portion of the printed circuit board, other than the wire bonding pads and the surface mount device mounting pads; (d) forming an electroless nickel immersion gold layer, composed of an electroless nickel plating layer and an electroless gold plating layer, on each of the wire bonding pads and surface mount device mounting pads, through electroless nickel plating and electroless gold plating; (e) removing the plating resist; and (f) forming a gold electroplating layer on the electroless nickel immersion gold layer of the surface mount device mounting pad to which a plating lead wire is connected, among the surface mount device mounting pads, the electroless nickel immersion gold layer of each of the wire bonding pads, and the ZIF connector pad, through gold electroplating.
6 . The method as set forth in claim 5 , wherein the electroless gold plating layer of the electroless nickel immersion gold layer has a thickness ranging from 0.01 μm to 0.1 μm.
7 . The method as set forth in claim 5 , wherein the electroless nickel plating layer of the electroless nickel immersion gold layer has a thickness ranging from 0.3 μm to 15 μm.
8 . The method as set forth in claim 5 , wherein the gold electroplating layer has a thickness ranging from 0.1 μm to 1.0 μm.Join the waitlist — get patent alerts
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