US2008254574A1PendingUtilityA1
Semiconductor device and a manufacturing method of the same
Est. expiryJul 14, 2025(expired)· nominal 20-yr term from priority
H10W 72/5522H10W 74/00H10W 90/291H10W 90/28H10W 90/24H10W 72/884H10W 72/5363H10W 72/536H10W 90/754H10W 90/752H10W 90/00H10W 90/732H10W 90/734H10W 70/611H10W 70/65H10W 90/701H10W 70/093H10W 70/60H05K 3/3485H05K 2201/09381H05K 3/3452H05K 2201/09418H05K 1/111H05K 2201/099H05K 2203/043H05K 2201/0989H05K 2201/10734Y02P70/50
46
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
By preparing a package substrate which has a plurality of lands of NSMD structure, and the output wiring and dummy wiring which were connected to each of the lands, and have been arranged mutually in the location of 180° symmetry, and printing solder by a printing method to the lands after the package assembly, the variation in the height of the solder coat between lands can be reduced, and improvement in the mountability of LGA (semiconductor device) is achieved.
Claims
exact text as granted — not AI-modified1 - 15 . (canceled)
16 . A method of manufacturing a semiconductor device, comprising the steps of:
(a) providing a wiring substrate having a main surface, a plurality of electrodes formed over the main surface, a back surface opposite to the main surface, an insulating film formed over the back surface, a plurality of lands formed over the back surface, and a first wiring and a second wiring connected to each land, wherein an edge part of each land is exposed from a corresponding opening of the insulating film, wherein the first and second wirings are arranged at locations substantially 180° from each other with respect to a perimeter of the land, and wherein a part of each of the first and the second wirings is exposed from the opening of the insulating film; (b) mounting a semiconductor chip over the main surface of the wiring substrate through a die-bonding material; (c) electrically connecting the semiconductor chip and the plurality of electrodes of the wiring substrate through a plurality of wires; (d) sealing the semiconductor chip and the plurality of wires; and (e) printing solder to the lands.
17 . A method of manufacturing a semiconductor device according to claim 16 , wherein
the plurality of lands constitute all of the lands formed over the back surface of the wiring substrate.
18 . A method of manufacturing a semiconductor device according to claim 16 , wherein
additional lands are formed over the back surface of the wiring substrate, and the first and the second wirings are provided only for lands arranged in locations corresponding to an edge part of the main surface of the semiconductor chip.
19 . A method of manufacturing a semiconductor device according to claim 16 , wherein
the first and the second wirings are provided only for one or more lands arranged furthest from a center of the wiring substrate in plan view.Join the waitlist — get patent alerts
Track US2008254574A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.