Tcp/ip processor and engine using rdma

Abstract

A TCP/IP processor and data processing engines for use in the TCP/IP processor is disclosed. The TCP/IP processor can transport data payloads of Internet Protocol (IP) data packets using an architecture that provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also provide packet inspection through Layer 7. The engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a TCP/IP session information database and may also store a storage information session database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory. An application running on an initiator or target can in certain instantiations register a region of memory, which is made available to its peer(s) for access directly without substantial host intervention through RDMA data transfer.

1 . A TCP/IP stack providing transport layer remote direct memory access capability for use in transporting information in active sessions or connections over IP networks, said stack providing an interface to the upper layer protocol functions in a host processor to carry data traffic, and performing at least one of the hardware implemented functions of:
 a. sending and receiving data, including upper layer data;   b. establishing transport sessions and session teardown functions;   c. executing error handling functions;   d. executing time-outs;   e. executing retransmissions;   f. executing segmenting and sequencing operations;   g. maintaining protocol information regarding said active transport sessions;   h. maintaining TCP/IP state information for each of said one or more session connections;   i. fragmenting and defragmenting data packets;   j. routing and forwarding data and control information;   k. sending to and receiving from a peer, memory regions reserved for RDMA;   l. recording said memory regions reserved for RDMA in an RDMA database and maintaining said database;   m. executing operations provided by RDMA capability;   n. executing security management functions;   o. executing policy management and enforcement functions;   p. executing virtualization functions;   q. communicating errors;   r. processing Layer 2 media access functions to receive and transmit data packets, validate the packets, handle errors, communicate errors and other Layer 2 functions;   s. processing physical layer interface functions;   t. executing TCP/IP checksum generation and verification functions;   u. processing Out of Order packet handling;   v. CRC calculation functions;   w. processing Direct Data Placement/Transfer;   x. Upper Layer Framing functions;   y. processing functions and interface to socket API's;   z. forming packet headers for TCP/IP for transmitted data and extraction of payload from received packets; and   aa. processing header formation and payload extraction for Layer 2 protocols of data to be transmitted and received data packets; respectively.   
   
   
       2 . The TCP/IP stack of  claim 1  further comprising memory for storing a database to maintain various information regarding said active sessions or connections and TCP/IP state information for each of said sessions or connections. 
   
   
       3 . The TCP/IP stack of  claim 1  further comprising an interface that includes circuitry for interfacing to at least one layer that is a wired or wireless Ethernet, MII, GMII, XGMII, XPF, XAUI, TBI, SON ET, DSL, POS, POS-PHY, SPI Interface, SPI-4 or other SPI derivative Interface, Infiniband, or FC layer. 
   
   
       4 . A TCP/IP processor engine having RDMA capability, said processor engine for processing Internet Protocol packets and comprising at least one of each of:
 a. an RDMA mechanism for performing RDMA data transfer;   b. a checksum hardware for performing checksum operations;   c. a data memory for storing data used in the TCP/IP processor engine;   d. an instruction memory for storing instructions used in the TCP/IP processor;   e. an instruction fetch mechanism for fetching said instructions;   f. an instruction decoder for decoding said instructions;   g. an instruction sequencer for sequencing said instructions;   h. a session database memory for storing TCP/IP session data; and   i. a session database memory controller for controlling said session database memory; and a host interface, or a fabric interface, or bus controller, or memory controller or combination of any of the foregoing for coupling to a host or a fabric.   
   
   
       5 . The TCP/IP processor engine of  claim 4  further comprising at least one of:
 a. a hash engine for performing hash functions;   b. a sequencer manager for sequencing operations;   c. a window operations manager for performing windowing operations to position packets within, and/or verify packets to be within, agreed windows;   d. a classification tag interpreter for interpreting classification tags;   e. a frame controller for controlling data framing;   f. an out of order manager for handling out of order data;   g. a register file for storing data;   h. a TCP state manager for managing TCP session states;   i. a CRC component for performing CRC operations;   j. an execution resource unit or ALU for data processing;   k. a TCP session database lookup engine for accessing session entries;   l. an SNACK engine for selective negative acknowledgment;   m. an SACK engine for selective positive acknowledgment;   n. a segmentation controller for controlling the segmentation of data;   o. a timer for event timing; and   p. a packet memory for storing packets.   
   
   
       6 . The combination of  claim 5  wherein said register file stores packet headers, pointers, contexts or session states or any combination thereof. 
   
   
       7 . A TCP/IP processor implemented in hardware and capable of implementing transport level RDMA functions, said processor including a session memory for storing session information for a plurality of sessions. 
   
   
       8 . A method, using a hardware TCP/IP processor capable of executing a transport layer RDMA protocol, of transferring data from a host processor to an output media interface of said host processor using said RDMA protocol, said method comprising said TCP/IP processor forming headers and forming segmentation for said data to be transferred. 
   
   
       9 . The method of  claim 8  wherein at least one of said headers is a header used for transporting data through a storage area network, a local area network, a metro area network, a system area network, a wireless local area network, a personal area network, a home network, a wide area network, or a combination of any of the foregoing. 
   
   
       10 . A TCP/IP processor having transport level RDMA capability for enabling TCP or other session oriented protocols, over IP networks, said processor comprising:
 a. an RDMA mechanism for performing RDMA data transfer   b. at least one TCP/IP processor engine for processing IP packets;   c. a session memory for storing session information;   d. at least one memory controller for controlling memory accesses;   e. at least one media interface for coupling to at least one network; and   f. a host interface for coupling to at least one host or a fabric interface for coupling to a fabric.   
   
   
       11 . The TCP/IP processor of  claim 10  further comprising at least one of:
 a. a packet processor engine for processing packets;   b. a classification processor for classifying IP packets;   c. a flow controller for controlling data flow;   a. a policy processor for applying policies;   e. a security processor for performing security operations;   f. a controller for control plane processing;   g. a packet scheduler;   h. a packet memory for storing packets; and   i. a connection manager or session controller for managing sessions.   
   
   
       12 . A TCP/IP processor having transport level RDMA capability for enabling TCP over IP networks, said processor including a TCP/IP stack providing TCP/IP protocol termination and origination, said processor comprising:
 a. an RDMA mechanism for performing RDMA data transfer;   b. at least one TCP/IP processor engine for processing IP packets;   c. a session memory for storing session information;   d. at least one memory controller for controlling memory accesses;   e. at least one media interface for coupling to at least one network; and   f. a host interface for coupling to at least one host or fabric interface for coupling to a fabric.   
   
   
       13 . The TCP/IP processor of  claim 12  further comprising at least one of:
 a. a packet processor engine for processing packets;   b. a classification processor for classifying IP packets;   c. a flow controller for controlling data flow;   d. a policy processor for applying policies;   e. a security processor for performing security operations;   f. a controller for control plane processing;   g. a packet scheduler for scheduling packets;   h. a packet memory for storing packets; and   i. a connection manager or session controller for managing TCP/IP sessions.   
   
   
       14 . A TCP/IP processor having transport level RDMA capability for enabling TCP over IP networks, said processor including a TCP/IP stack providing TCP/IP protocol termination and origination, said stack providing an interface to sockets layer functions in a host processor to transport data traffic, said processor comprising:
 a. an RDMA mechanism for performing RDMA data transfer;   b. at least one TCP/IP processor engine for processing IP packets;   c. a session memory for storing session information;   d. at least one memory controller for controlling memory accesses;   e. a media interface for coupling to at least one network; and   f. a host interface for coupling to at least one host or fabric interface for coupling to a fabric.   
   
   
       15 . The TCP/IP processor of  claim 14  further comprising at least one of:
 a. a packet processor engine for processing packets;   b. a classification processor for classifying IP packets;   c. a flow controller for controlling data flow;   d. a policy processor for applying policies;   e. a security processor for performing security operations;   f. a controller for control plane processing;   g. a packet scheduler for scheduling packets;   h. a packet memory for storing packets; and   i. a connection manager or session controller for managing TCP/IP sessions.   
   
   
       16 . The TCP/IP processor of  claim 14  wherein said processor operates in multiple stages, comprising one or more stages of:
 a. receiving incoming IP packets;   b. providing security processing for said incoming IP packets if necessary;   c. classifying said incoming IP packets;   d. scheduling IP packets for processing;   e. executing data and/or protocol processing operations on IP packets;   f. providing direct memory access for transferring data/packets to or from the memory of a system external to said processor;   g. executing protocol processing operations on data or commands forming IP packets;   h. providing security processing for outgoing IP packets if necessary; and   i. transmitting outgoing IP packets onto a network; wherein each of said stages is capable of operating on different IP packets concurrently.   
   
   
       17 . The TCP/IP processor of  claim 12  wherein said processor operates in multiple stages, comprising one or more stages of:
 a. receiving incoming IP packets;   b. providing security processing for said incoming IP packets if necessary;   c. classifying said incoming IP packets;   d. scheduling IP packets for processing;   e. executing data and/or protocol processing operations on IP packets;   f. providing direct memory access for transferring data/packets to or from the memory of a system external to said processor;   g. executing protocol processing operations on data or commands forming IP packets;   h. providing security processing for outgoing IP packets if necessary; and   i. transmitting outgoing IP packets onto a network; wherein each of said stages is capable of operating on different IP packets concurrently.