Transmit clock generator

Abstract

A transmit clock generator includes a first local clock generator and a second local clock generator, each receiving an external PLL clock signal and respectively generating first and second divided clock signals. A synchronization signal is applied to the first local clock generator and second local clock generator during a clock training period to enforce a phase relationship between the first and second divided clock signals. The synchronization signal includes at least one synchronization pulse that is applied to the first local clock generator and second local clock generator during the clock training period.

1 - 4 . (canceled) 
   
   
       5 . A transmit clock generator for clock generation for a transmitter comprising:
 a first local clock generator and a second local clock generator, each receiving an external PLL clock signal and respectively generating first and second divided clock signals;   a synchronization signal for enforcing a phase relationship between the first and second divided clock signals; said synchronization signal being applied to said first local clock generator and said second local clock generator during a clock training period; said synchronization signal including at least one synchronization pulse being applied to the first local clock generator and second local clock generator during the clock training period; and   a data clock sampler for generating said synchronization signal; said data clock sampler receiving and sampling a data synchronous clock signal for providing sample outputs, and said data clock sampler being clocked by the external PLL clock; said data clock sampler including a first master latch receiving said data synchronous clock signal and a first slave latch coupled to said master latch, said first master and first slave latches being connected to a second master and second slave latch for resolving metastability by double latching sampled data clock inputs; and   a plurality of latches being series connected to said master and slave latches for pipelining sample outputs.   
   
   
       6 . (canceled) 
   
   
       7 . A transmit clock generator for clock generation for a transmitter comprising:
 a first local clock generator and a second local clock generator, each receiving an external PLL clock signal and respectively generating first and second divided clock signals;   a synchronization signal for enforcing a phase relationship between the first and second divided clock signals; said synchronization signal being applied to said first local clock generator and said second local clock generator during a clock training period; said synchronization signal including at least one synchronization pulse being applied to the first local clock generator and second local clock generator during the clock training period; and   a data clock sampler for generating said synchronization signal; said data clock sampler receiving and sampling a data synchronous clock signal for providing sample outputs, and said data clock sampler being clocked by the external PLL clock;   said sample outputs of the data clock sampler being applied to a synchronization pulse generator; said synchronization pulse generator for generating synchronization pulses; said synchronization pulse generator detecting rising edge samples from the data clock sampler and outputs rising edge synchronization pulses.   
   
   
       8 . A transmit clock generator as recited in  claim 7  includes a gated synchronization repower tree, and said gated synchronization repower tree receiving and repowering said rising edge synchronization pulses. 
   
   
       9 . A transmit clock generator as recited in  claim 8  wherein said gated synchronization repower tree is gated by a synchronization control signal generated by a clock synchronization control; said synchronization control signal for allowing at least one synchronization pulse to be applied to the first local clock generator and second local clock generator only during the clock training period. 
   
   
       10 . A transmit clock generator as recited in  claim 9  wherein said clock synchronization control establishes the clock training period responsive to an applied reset signal indicating proper power to the transmitter has been established and no reset conditions are pending and an applied input indicating valid synchronization pulses are being produced. 
   
   
       11 . A transmit clock generator as recited in  claim 9  wherein said clock synchronization control includes an OR gate receiving said synchronization pulses and feedback of the synchronization control signal; said OR gate coupled to an input of an AND gate and a reset signal applied to another input of said AND gate, said AND gate coupled to a first latch of a latch pair; said latch pair providing the synchronization control signal, said external PLL clock signal applied to respective clock inputs of said latch pair. 
   
   
       12 . A transmit clock generator as recited in  claim 11  wherein said reset signal is generated by a clock initialization and reset functional block; said clock initialization and reset functional block receiving a power good signal and a transmitter reset signal; said clock initialization and reset functional block including an AND gate for combining said received signals. 
   
   
       13 . A transmit clock generator as recited in  claim 6  wherein said synchronization pulse generator includes an AND gate receiving sample outputs of a first pipelined latch pair and receiving sample outputs of a second pipelined latch pair of said data clock sampler. 
   
   
       14 . A transmit clock generator as recited in  claim 9  wherein said gated synchronization repower tree includes an AND gate having an input receiving said synchronization control signal and an input receiving said rising edge synchronization pulses. 
   
   
       15 - 19 . (canceled)