Semiconductor memory devices having strapping contacts

Abstract

Semiconductor memory devices having strapping contacts with an increased pitch are provided. The semiconductor memory devices include cell regions and strapping regions between adjacent cell regions in a first direction on a semiconductor substrate. Active patterns extend in the first direction throughout the cell regions and strapping regions and are spaced apart from one another in a second direction intersecting the first direction. First interconnection lines extend in the first direction throughout the cell regions and the strapping regions and are spaced apart from one another in the second direction while overlapping with the active patterns. Second interconnection lines extend in the second direction to intersect the active patterns and the first interconnection lines in the cell regions. The second interconnection lines are spaced apart from one another in the first direction. Memory cells are positioned at intersection portions of the first and second interconnection lines in the cell regions. Strapping contacts are in the strapping regions and configured such that the active patterns contact with the first interconnection lines through the strapping contacts.

1 . A semiconductor memory device, comprising:
 a plurality of cell regions and a plurality of strapping regions between adjacent cell regions on a semiconductor substrate, wherein the cell regions and strapping regions extend in a first direction;   a plurality of active patterns extending in the first direction throughout the cell regions and strapping regions, wherein the plurality of active patterns are spaced apart from one another in a second direction intersecting the first direction;   a plurality of first interconnection lines extending in the first direction throughout the cell regions and the strapping regions, wherein the plurality of first interconnection lines are spaced apart from one another in the second direction and overlap with the active patterns;   a plurality of second interconnection lines extending in the second direction and intersecting the active patterns and the first interconnection lines in the cell regions, wherein the plurality of second interconnection lines are spaced apart from one another in the first direction;   a plurality of memory cells each at intersection portions of the first and second interconnection lines in the cell regions; and   a plurality of strapping contacts in the strapping regions, wherein the active patterns contact the first interconnection lines through the strapping contacts and the strapping contacts in each of the strapping regions are on at least one of the active patterns.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein the strapping contacts are in a zigzag form. 
     
     
         3 . The semiconductor memory device of  claim 2 , wherein the first interconnection lines includes word lines and the second interconnection lines includes bit lines. 
     
     
         4 . The semiconductor memory device of  claim 2 , wherein the strapping contacts in each of the strapping regions are on the active patterns in the zigzag form in the second direction. 
     
     
         5 . The semiconductor memory device of  claim 2 , wherein the strapping contacts in adjacent strapping regions are on the active patterns in the zigzag form in the second direction. 
     
     
         6 . The semiconductor memory device of  claim 2 , wherein the active patterns include impurity regions doped with predetermined conductive type impurities in the semiconductor substrate. 
     
     
         7 . The semiconductor memory device of  claim 2 , wherein the memory cells include phase-change random access memory (PRAM) cells. 
     
     
         8 . The semiconductor memory device of  claim 1 , further comprising a plurality of unit cell groups each having a number of the memory cells, i×j, in the first and second directions, wherein i represents a number of the second interconnection lines and j represents a number of the active patterns in each respective unit cell group. 
     
     
         9 . The semiconductor memory device of  claim 8 , wherein the first interconnection lines includes word lines and the second interconnection lines includes bit lines. 
     
     
         10 . The semiconductor memory device of  claim 8 , wherein the strapping contacts are in every other strapping region of each active pattern in the first direction. 
     
     
         11 . The semiconductor memory device of  claim 10 , wherein the strapping contacts are along every 2× memory cells on each active pattern in the first direction, x representing a number of the bit lines between the strapping contacts in each active pattern. 
     
     
         12 . The semiconductor memory device of  claim 8 , wherein the strapping contacts in each strapping region are on every other active pattern in the second direction. 
     
     
         13 . The semiconductor memory device of  claim 8 , further comprising:
 a first isolation layer that isolates adjacent first interconnection lines of adjacent unit cell groups in the second direction; and   a second isolation layer that isolates adjacent first interconnection lines in the second direction within each of the unit cell groups, wherein the second isolation layer has a size smaller than the first isolation layer.   
     
     
         14 . The semiconductor memory device of  claim 8 , wherein the active patterns include impurity regions doped with predetermined conductive type impurities in the semiconductor substrate. 
     
     
         15 . The semiconductor memory device of  claim 8 , wherein the memory cells include phase-change random access memory (PRAM) cells. 
     
     
         16 . The semiconductor memory device of  claim 8 , wherein at least two of the strapping contacts in each of the strapping regions are on a same line. 
     
     
         17 . The semiconductor memory device of  claim 16 , wherein the strapping contacts on each active pattern are in each strapping region in the first direction. 
     
     
         18 . The semiconductor memory device of  claim 17 , wherein the strapping contacts are along every x memory cells in each of the active patterns in the first direction, x representing a number of the bit lines between the strapping contacts in each active pattern. 
     
     
         19 . The semiconductor memory device of  claim 16 , wherein the strapping contacts in each strapping region cross each other in adjacent active patterns in the second direction. 
     
     
         20 . The semiconductor memory device of  claim 16 , further comprising:
 a first isolation layer that isolates adjacent first interconnection lines of adjacent unit cell groups in the second direction; and   a second isolation layer that isolates adjacent first interconnection lines in the second direction within each of the unit cell groups, wherein the second isolation layer has a size smaller than the first isolation layer.   
     
     
         21 . The semiconductor memory device of  claim 16 , wherein the active patterns include impurity regions doped with predetermined conductive type impurities in the semiconductor substrate.