Tileable field-programmable gate array architecture

Abstract

An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

1 . (canceled) 
   
   
       2 . An apparatus including a field-programmable gate array (FPGA), the FPGA comprising:
 a first FPGA tile that includes:
 a plurality of functional groups (FGs) arranged in rows and columns, each configurable to perform logic operations, each FG having a first, second, and third set of input ports and a first, second, and third set of output ports; 
 a plurality of interface groups (IGs) surrounding the plurality of FGs such that one IG is positioned at each end of each row and column; 
 a primary routing structure comprising a first set of routing conductors disposed within said first FPGA tile programmably coupled to said first set of output ports of said FGs, configured to receive signals, route signals within said first FPGA tile, and provide said signals to said first set of input ports of said FGs; 
 a secondary routing structure comprising a second set of routing conductors that are: disposed across said first FPGA tile independent of said first routing structure, coupled to said second set of output ports of said FGs, configured to receive, select and route signals around said first FPGA tile and within first FPGA tile, and provide said signals to said second set of input ports of said FGs; and 
 a tertiary routing structure comprising a third set of routing conductors that are: disposed across said first FPGA tile independent of said first and second routing structure, coupled to said third set of output ports of said FGs, and employing a plurality of tracks and a plurality of switches to receive signals, route signals around said first FPGA tile and within said first FPGA tile, and provide said signals to said third set of input ports of said FGs when said first set of routing conductors cannot be used. 
   
   
   
       3 . The apparatus in accordance with  claim 2 , wherein each of the IGs further comprises:
 a plurality of output multiplexers configured to select signals received from the first and second routing structures and provide the selected signals to outside of the FPGA tile.   
   
   
       4 . The apparatus in accordance with  claim 2 , wherein each of the IGs further comprises:
 a plurality of input multiplexers configured to select signals received from outside of the FPGA tile and provide the selected signals to the first and second routing structures inside of the FPGA tile.   
   
   
       5 . The apparatus in accordance with  claim 4 , wherein the apparatus further comprises:
 a plurality of input/output pads (I/Os) and each of the input multiplexers is coupled directly to at least one of the I/Os.   
   
   
       6 . The apparatus in accordance with  claim 2 , wherein the FPGA further comprises:
 a second FPGA tile that includes a plurality of FGs, a plurality of IGs, and a first, second, and third set of routing conductors arranged in a manner substantially similar to the first FPGA tile, wherein at least one IG of the first FPGA tile is coupled to at least one IG of the second FPGA tile.   
   
   
       7 . The apparatus in accordance with  claim 6 , wherein the FPGA further comprises:
 a third FPGA tile that includes a plurality of FGs, a plurality of IGs, and a first, second, and third set of routing conductors arranged in a manner substantially similar to the first FPGA tile, wherein at least one IG of the first FPGA tile is coupled to at least one IG of the third FPGA tile.   
   
   
       8 . The apparatus in accordance with  claim 2 , wherein:
 the apparatus further comprises a system-on-a-chip (SOC).   
   
   
       9 . The apparatus in accordance with  claim 2 , wherein each of the FGs further comprises:
 a multiplexer configured to select one of the primary output signals as an FG secondary routing signal.   
   
   
       10 . The apparatus in accordance with  claim 2 , wherein:
 each of the IGs further comprises a first, second, and third input port and a first, second, and third output port;   the tertiary routing structure is coupled to and provides signals to the third input ports of at least one of the IGs; and   the tertiary routing structure is coupled to and receives signals from the third output port of at least one of the IGs.   
   
   
       11 . The apparatus in accordance with  claim 10 , wherein each of the IGs further comprises:
 a multiplexer configured to select a signal received from outside of the FPGA tile as an IG tertiary routing signal, wherein the tertiary routing structure is configured to select and route the IG tertiary routing signal around the first FPGA tile.   
   
   
       12 . The apparatus in accordance with  claim 10 , wherein each of the IGs further comprises:
 a multiplexer configured to select a signal received from the first routing structure, second routing structure, and third routing structure, and transmit the signal outside the first FPGA tile.   
   
   
       13 . The apparatus in accordance with  claim 2 , wherein:
 said plurality of tracks intersect at a plurality of interconnect areas.   
   
   
       14 . The apparatus in accordance with  claim 13  wherein:
 at least one of said plurality of interconnect areas is fully populated with said plurality of switches.   
   
   
       15 . The apparatus in accordance with  claim 13  wherein:
 at least one of said plurality of interconnect areas is not fully populated with said plurality of switches.   
   
   
       16 . The apparatus in accordance with  claim 2  wherein:
 each of the plurality of switches comprises a transistor switch coupled to and controlled by a memory cell.