Sram cell with asymmetrical transistors for reduced leakage

Abstract

A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabrication of asymmetrical pass transistors comprises forming a dielectric region on a surface of a substrate having a first conductivity type. A gate region having a length and a width is formed on the dielectric region. Source and drain extension regions having a second conductivity type are formed in the substrate on opposite sides of the gate region. A first pocket impurity region having a first concentration and the first conductivity type is formed adjacent the source. A second pocket impurity region having a second concentration and the first conductivity type may be formed adjacent the drain. If formed, the second concentration is smaller than the first concentration, reducing the gate induced drain leakage current.

1 - 7 . (canceled) 
   
   
       8 . An SRAM memory cell, comprising:
 a storage node;   a supply node; and   an asymmetrical load transistor connected between the storage node and the supply node, wherein the asymmetrical load transistor has a first drain leakage current when said supply node is positive with respect to the storage node and said asymmetrical load transistor has a second drain leakage current of greater magnitude than the first drain leakage current when the supply node is negative with respect to the storage node.   
   
   
       9 . The SRAM memory cell of  claim 8 , wherein the asymmetrical load transistor comprises a more heavily doped pocket implant region on the supply node side relative to the storage node side. 
   
   
       10 . The SRAM memory cell of  claim 9 , wherein said asymmetrical load transistor comprises a source region and a drain region of a first conductivity type and wherein said pocket implant region is of a second conductivity type, opposite said first conductivity type. 
   
   
       11 - 13 . (canceled) 
   
   
       14 . A memory cell; comprising:
 a first supply voltage terminal;   a first storage node;   a second supply voltage terminal;   a second storage node;   a first transistor having a source and drain and formed on a substrate having a first conductivity type, the first transistor having the source coupled to the first supply voltage terminal and the drain coupled to the first storage node; and   a second transistor having a source and drain and formed on a substrate having a second conductivity type, the second transistor having the drain coupled to the second storage node and the source coupled to the second supply voltage terminal, wherein at least one of the first and second transistors has a higher dopant concentration of a respective substrate conductivity type adjacent a respective source than adjacent a respective drain.   
   
   
       15 . The memory cell of  claim 14  in which the substrate of the first conductivity type is formed on a substrate of the second conductivity type.