Integrated circuit structures having a boron etch-stop layer and methods, devices and systems related thereto

Abstract

An integrated circuit structure comprising a boron etch-stop layer on a surface of the integrated circuit structure having a full-width half-maximum (FWHM) thickness value less than 100 nanometers, wherein the boron etch-stop layer is substantially free of germanium and carbon. In one embodiment, the boron etch-stop layer has a FWHM thickness value less than 20 nanometers and may contain added germanium or carbon. Systems and devices containing same are also disclosed. Chemical vapor deposition (CVD) may be used to form the boron etch-stop layer.

1 . An integrated circuit structure comprising a boron etch-stop layer located on a surface of the integrated circuit structure and having a full-width half-maximum (FWHM) thickness value less than 100 nanometers, wherein the boron etch-stop layer is substantially free of germanium and carbon. 
     
     
         2 . The integrated circuit structure of  claim 1  comprising a substrate selected from silicon, silicon-germanium, and silicon carbide. 
     
     
         3 . The integrated circuit structure of  claim 1  comprising a film selected from epitaxial silicon, epitaxial silicon-carbide, and epitaxial silicon-germanium. 
     
     
         4 . The integrated circuit structure of  claim 1  comprising a deposited silicon film. 
     
     
         5 . The integrated circuit structure of  claim 1  wherein the boron etch-stop layer is less than about 20 nanometers in thickness when measured as a FWHM value. 
     
     
         6 . (canceled) 
     
     
         7 . The integrated circuit structure of  claim 5  further comprising a carbon concentration of between 10 18  and 10 21  atoms per cubic centimeter in the boron etch-stop layer. 
     
     
         8 . The integrated circuit structure of  claim 5  further comprising a germanium concentration fraction of less than one percent to about 20 percent in the boron etch-stop layer. 
     
     
         9 . The integrated circuit structure of  claim 5  comprising a silicon-based semiconductor structure. 
     
     
         10 . The integrated circuit structure of  claim 9  wherein the silicon-based semiconductor structure is a compound semiconductor film selected from a Group II through Group VI semiconductor compound and combinations thereof. 
     
     
         11 . The integrated circuit structure of  claim 10  wherein the semiconductor compound is selected from SiGe, GaAs, InGaAs, ZnSe, CdSe, CdTe, and combinations thereof. 
     
     
         12 . An electronic device comprising:
 an integrated circuit structure; and   a boron etch-stop layer located on the integrated circuit structure and having a full-width half-maximum (FWHM) thickness value of less than 20 nanometers.   
     
     
         13 . The electronic device of  claim 12  comprising a heterojunction bipolar transistor. 
     
     
         14 . The electronic device of  claim 12  comprising a bond-and-etch-back silicon-on-insulator (BESOI) substrate. 
     
     
         15 . The electronic device of  claim 14  wherein the BESOI substrate is a complementary metal-oxide semiconductor (CMOS) device. 
     
     
         16 . The electronic device of  claim 12  further comprising a carbon concentration of between 10 18  and 10 21  atoms per cubic centimeter in the boron etch-stop layer. 
     
     
         17 . The electronic device of  claim 12  further comprising a germanium concentration fraction of less than one percent to about 20 percent in the boron etch-stop layer. 
     
     
         18 . The electronic device of  claim 12  further comprising one or more carbon-doped spacers on the electronic device to provide a source of carbon atoms for the etch-stop layer. 
     
     
         19 . A system comprising:
 an integrated circuit structure;   a boron etch-stop layer located on a surface of the integrated circuit structure and having a full-width half-maximum (FWHM) thickness value of less than 20 nanometers; and   a liquid crystal display or data storage coupled to the integrated circuit structure.   
     
     
         20 . The system of  claim 19  wherein the boron etch-stop layer further comprises an additional elemental concentration selected from a carbon concentration of between 10 18  and 10 21  atoms per cubic centimeter, a germanium concentration fraction of less than one percent to about 20 percent, and combinations thereof. 
     
     
         21 . The system of  claim 20  wherein the integrated circuit structure is a silicon-based semiconductor structure. 
     
     
         22 . A method comprising:
 flowing a carrier gas over an integrated circuit structure in a chemical vapor deposition chamber;   flowing a silicon precursor gas over the integrated circuit structure in the deposition chamber; and   flowing a boron precursor gas over the integrated circuit structure in the deposition chamber to form a boron etch-stop layer on the integrated circuit structure which is less than 100 nanometers in thickness when measured as a full-width half-maximum (FWHM) value.   
     
     
         23 . The method of  claim 22  wherein the carrier gas is selected from hydrogen, nitrogen, argon, helium, xenon, fluorine, and combinations thereof. 
     
     
         24 . The method of  claim 23  wherein the boron etch-stop layer is less than about 20 nanometers in thickness when measured as a FWHM value. 
     
     
         25 . The method of  claim 22  wherein the silicon precursor gas is silane or disilane flowing at between five (5) standard cubic centimeters per minute (sccm) and 1000 sccm. 
     
     
         26 . The method of  claim 22  wherein the boron precursor gas is diborane or boron trichloride flowing at between five (5) and 1000 sccm. 
     
     
         27 . The method of  claim 22  further comprising:
 flowing a carbon precursor gas over the integrated circuit structure; and   flowing a germanium precursor gas over the integrated circuit structure to limit a diffusivity value of boron atoms within the boron etch-stop layer.   
     
     
         28 . The method of  claim 27  wherein the carbon precursor gas is methyl silane flowing at between five (5) and 1000 sccm and the germanium precursor gas is germanium tetrahydride flowing at between five (5) and 1000 sccm. 
     
     
         29 . The method of  claim 27  wherein temperatures in the chemical vapor deposition chamber are between 550 and 750° C. and pressures are between one (1) and 100 Torr, and the integrated circuit structure is a bond-and-etch-back silicon-on-insulator (BESOI) wafer comprised of a silicon device wafer and a silicon handle wafer, wherein the silicon device wafer includes a first silicon layer covered by the boron etch-stop layer and a second silicon layer, and the silicon device wafer includes a lower silicon dioxide layer covered by a silicon substrate layer and an upper silicon dioxide layer, wherein the method further comprises:
 diffusion bonding the silicon device wafer to the silicon handle wafer to form a BESOI wafer having a diffusion bond;   thermally annealing the BESOI wafer to strengthen the diffusion bond; and   thinning the BESOI wafer to remove most of the second silicon layer.   
     
     
         30 . The method of  claim 29  wherein the thinning step is followed by an etching step to remove a remaining portion of the second silicon layer up to the boron etch-stop layer. 
     
     
         31 . The method of  claim 29  wherein the thinning step is followed by a hydrogen implantation and separation step. 
     
     
         32 . The method of  claim 29  wherein the annealing occurs at approximately 1000° C. for about 10 seconds or more.