Group III-V Semiconductor device and method for producing the same

Abstract

A Group III-V semiconductor device bonded to a conductive support substrate, which device has a side surface whose surface layer has a high-resistance region formed through ion implantation.

1 . A Group III-V semiconductor device bonded to a conductive support substrate, which device has a side surface whose surface layer has a high-resistance region formed through ion implantation. 
   
   
       2 . A semiconductor device as described in  claim 1 , which is bonded to the support substrate by means of a low-melting-point metal layer. 
   
   
       3 . A semiconductor device as described in  claim 2 , wherein the low-melting-point metal layer comprises at least one selected from a group consisting of Au—Sn, Au—Si, Ag—Sn—Cu, and Sn—Bi. 
   
   
       4 . A semiconductor device as described in  claim 1 , which is bonded to the support substrate by means of a non-solder layer. 
   
   
       5 . A semiconductor device as described in  claim 4 , wherein the non-solder layer comprises at least one selected from a group consisting of Au, Sn, and Cu. 
   
   
       6 . A semiconductor device as described in  claim 1 , which is formed into an inverted tapered structure in which the device has a cross-sectional area gradually decreasing toward the support substrate. 
   
   
       7 . A semiconductor device as described in  claim 1 , which has a p-electrode bonded to the support substrate, and the p-electrode is formed on the entire top surface of the support substrate. 
   
   
       8 . A semiconductor device as described in  claim 1 , which has a top surface whose surface layer has, at least in the vicinity of the side surface, a high-resistance region formed through ion implantation. 
   
   
       9 . A semiconductor device as described in  claim 1 , which has a top surface having thereon, at least in the vicinity of the side surface, an insulating film formed of a dielectric material. 
   
   
       9 . A semiconductor device as described in  claim 1 , which has a top surface having thereon, at least in the vicinity of the side surface, an insulating film formed of a dielectric material. 
   
   
       10 . A semiconductor device as described in  claim 1 , wherein the support substrate is formed through plating. 
   
   
       11 . A semiconductor device as described in  claim 1 , which is a Group III nitride semiconductor device. 
   
   
       12 . A semiconductor device as described in  claim 1 , which is a light-emitting device. 
   
   
       13 . A method for producing a Group III-V semiconductor device, the method comprising:
 forming, on a base, a plurality of semiconductor devices isolated from one another;   forming, through ion implantation, a high-resistance region in a surface layer of a side surface of each semiconductor device;   after formation of the high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on the top surface of the semiconductor device;   bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer; and   removing the base through the laser lift-off process.   
   
   
       14 . A semiconductor device production method as described in  claim 13 , wherein the side surface of the semiconductor device is formed to be inclined so that the device has a cross-sectional area gradually increasing toward the base, and ion implantation is performed along a direction normal to the main plane of the base. 
   
   
       15 . A semiconductor device production method as described in  claim 13 , wherein ion implantation is performed along a direction normal to the main plane of the base at an acceleration voltage which allows the implanted ions to reach the base. 
   
   
       16 . A semiconductor device production method as described in  claim 13 , which includes, after removal of the base, performing ion implantation into a portion of the surface of the semiconductor device which surface has previously bonded to the base, the portion is in the vicinity of the side surface. 
   
   
       17 . A semiconductor device production method as described in  claim 13 , which includes, after removal of the base, forming an n-electrode on the surface of the semiconductor device which surface has previously bonded to the base, and performing ion implantation into the surface of the semiconductor device through the n-electrode, which serves as a mask. 
   
   
       18 . A semiconductor device production method as described in  claim 13 , which includes, after removal of the base, forming a dielectric material insulating film on a portion of the surface of the semiconductor device which surface has previously bonded to the base, the portion being in the vicinity of the side surface. 
   
   
       19 . A method for producing a Group III-V semiconductor device, the method comprising:
 forming a Group III-V semiconductor layer on a base;   forming a high-resistance region in a surface layer of a predetermined portion of the top surface of the semiconductor layer through ion implantation at an acceleration voltage which allows the implanted ions to reach the base;   dividing the semiconductor layer, through the high-resistance region, into semiconductor devices isolated from one another;   after formation of the high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on the top surface of each semiconductor device;   bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer; and   removing the base through the laser lift-off process.   
   
   
       20 . A semiconductor device production method as described in  claim 15 , wherein ion implantation is performed at a plurality of times at different acceleration voltages. 
   
   
       21 . A method for producing a Group III-V semiconductor device, the method comprising:
 forming a Group III-V semiconductor layer on a base;   forming a first high-resistance region in a surface layer of a predetermined portion of the top surface of the semiconductor layer through ion implantation at an acceleration voltage which does not allow the implanted ions to reach the base;   after formation of the first high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on the top surface of the semiconductor layer;   bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer;   removing the base through the laser lift-off process; and   forming, in addition to the first high-resistance region, a second high-resistance region in a surface layer of a predetermined portion of the surface of the semiconductor layer which surface has previously bonded to the base, the portion corresponding to the first high-resistance region, through ion implantation at an acceleration voltage which allows the implanted ions to reach the first high-resistance region; and   dividing the semiconductor layer, through the first and second high-resistance regions, into semiconductor devices isolated from one another.   
   
   
       22 . A semiconductor device production method as described in  claim 13 , wherein the low-melting-point metal layer comprises at least one selected from a group consisting of Au—Sn, Au—Si, Ag—Sn—Cu, and Sn—Bi. 
   
   
       23 . A semiconductor device production method as described in  claim 13 , wherein the semiconductor device is a Group III nitride semiconductor device. 
   
   
       24 . A semiconductor device production method as described in  claim 13 , wherein the semiconductor device is a light-emitting device.