Design structure for radiation hardened programmable phase frequency divider circuit

Abstract

A design structure embodied in a machine readable medium includes information for designing, manufacturing and/or testing a programmable phase frequency divider circuit implemented in CMOS technology for space applications. The programmable phase frequency divider consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division ratios from 1 to 8. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU'S. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit.

1 . A design structure embodied in a machine readable medium for designing, manufacturing or testing a radiation hardened programmable phase frequency divider circuit, the programmable phase frequency divider circuit comprising:
 a plurality of radiation hardened D-type flip flops each having a clock input connected to a common clock source, first and second data inputs, first and second complementary data inputs, first and second data outputs, and first and second complementary data outputs;   a first combinational logic block connected to the first data inputs, first complementary data inputs, first data outputs and first complementary data outputs of the plurality of D-type flip flops;   a second combinational logic block identical to the first combinational logic block, and connected to the second data inputs, second complementary data inputs, second data outputs and second complementary data outputs of the plurality of D-type flip flops; and;   a third combinational logic block connected to the first combinational logic block for outputting a pulse train representing the clock source frequency divided in accordance with a division number inputted to the first and second combinational logic blocks,   wherein operation of each of the D-type flip flop is immune to a single event upset affecting at most one of its four data inputs.   
   
   
       2 . The design structure of  claim 1 , wherein the data inputs, DIN, and the complementary inputs, DINB, generated by the first and second combinational logic blocks are related to the data outputs and the complementary data outputs from the D-type flip flops by the equations:
 DIN=Function (Un, Un−1, . . . , U 0 ); and   DINB=Function (Vn, Vn−1, . . . , VO),   where Ui and Vi are respectively the data output and the complementary data output of the ith D-type flip flop.   
   
   
       3 . The design structure of  claim 1 , wherein each of the radiation hardened D-type flip flops is comprised of:
 a master latch having a clock input, first and second data inputs, first and second complementary data inputs, first and second data outputs, and first and second complementary data outputs; and   a slave latch having first and second data inputs, first and second complementary data inputs, first and second data outputs, and first and second complementary data outputs,   wherein   the clock input, first and second data inputs, and first and second complementary data inputs of the master latch serve respectively as the clock input, first and second data inputs, and first and second complementary data inputs of the D-type flip-flop,   the first data output and the first complementary data output of the master latch are connected respectively to the first data input and the first complementary data input of the slave latch,   the second data output and the second complementary data output of the master latch are connected respectively to the second data input and the second complementary data input of the slave latch, and   the first and second data outputs, and first and second complementary data outputs of the slave latch serve respectively as the first and second data outputs, and first and second complementary data outputs of the D-type flip-flop.   
   
   
       4 . The design structure of  claim 3 , wherein each radiation hardened master latch is comprised of:
 a first master latch half circuit having a clock input, first and second data inputs, first and second complementary data inputs, a feedback input, a complementary feedback input, a data output, and a complementary data output; and   a second master latch half circuit identical to the first master latch half circuit and having a clock input, first and second data inputs, first and second complementary data inputs, a feedback input, a complementary feedback input, a data output, and a complementary data output,   wherein   the respective clock inputs of the first and second master latch half circuits are connected together in parallel, and serve as the clock input to the master latch,   the respective first and second data inputs and first and second complementary data inputs of the first and second master latch half circuits are connected together in parallel, and serve respectively as the first and second data inputs and first and second complementary data inputs of the master latch,   the data output and the complementary data output of the first master latch half circuit are connected respectively to the feedback input and the complementary feedback input of the second master latch half circuit,   the data output and the complementary data output of the second master latch half circuit are connected respectively to the feedback input and the complementary feedback input of the first master latch half circuit.   the data output and the complementary data output of the first master latch half circuit serve respectively as the first data output and the first complementary data output of the master latch, and   the data output and the complementary data output of the second master latch half circuit serve respectively as the second data output and the second complementary data output of the master latch.   
   
   
       5 . The design structure of  claim 4 , wherein each of the master latch half circuits is comprised of:
 first and second pre-charging transistors each having one drain-source region coupled to a high voltage source and the other source-drain region coupled to the data output;   third and fourth pre-charging transistors each having one drain-source region coupled to the high voltage source and the other source-drain region coupled to the complementary data output;   a first equalization transistor having one drain-source region coupled to the data output and the other drain source region coupled to the complementary data output, the gates of first equalization transistor and the second and third pre-charging transistors all being coupled to the clock input through a first inverter;   first and second latch transistors each having one drain-source region coupled to the data output and the other source-drain region coupled to a first data node;   third and fourth latch transistors each having one drain-source region coupled to the complementary data output and the other source-drain region coupled to a second data node, the gates of the third and second latch transistors being cross coupled to the data output and the complementary data output, respectively, the gates of both the fourth latch transistor and the fourth pre-charging transistor being coupled to the feedback input, and the gates of both the first latch transistor and the first pre-charging transistor being coupled to the complementary feedback input;   a first clocking transistor having one drain-source region coupled to ground potential, the other drain-source region coupled to a first clocking node and the gate coupled to the clock input through a second inverter;   a second clocking transistor having one drain-source region coupled to ground potential, the other drain-source region coupled to a second clocking node and the gate coupled to the gate of the first clocking transistor;   a first data input transistor having one drain-source region coupled to the first data node, the other drain-source region coupled to the first clocking node and the gate coupled to the first complementary data input;   a second data input transistor having one drain-source region coupled to the first data node, the other drain-source region coupled to the second clocking node and the gate coupled to the second complementary data input;   a third data input transistor having one drain-source region coupled to the second data node, the other drain-source region coupled to the second clocking node and the gate coupled to the second data input;   a fourth data input transistor having one drain-source region coupled to the second data node, the other drain-source region coupled to the first clocking node and the gate coupled to the first data input;   a second equalization transistor having one drain-source region coupled to the first data node, the other drain-source region coupled to the second data node and the gate coupled to the high potential.   
   
   
       6 . The design structure of  claim 3 , wherein each radiation hardened slave latch is comprised of:
 a first slave latch half circuit having first and second data inputs, first and second complementary data inputs, a feedback input, a complementary feedback input, a data output, and a complementary data output; and   a second slave latch half circuit identical to the first slave latch half circuit and having first and second data inputs, first and second complementary data inputs, a feedback input, a complementary feedback input, a data output, and a complementary data output,   wherein   the first data input and the first complementary data input of the first slave latch half circuit are respective connected in parallel with second data input and the second complementary data input of the second slave latch half circuit, and serve respectively as the second data input and second complementary data input of the slave latch,   the second data input and the second complementary data input of the first slave latch half circuit are respectively connected in parallel with the first data input and the first complementary data input of the second slave latch half circuit, and serve respectively as the first data input and first complementary data input of the slave latch,   the data output and the complementary data output of the first slave latch half circuit are connected respectively to the feedback input and the complementary feedback input of the second slave latch half circuit,   the data output and the complementary data output of the second slave latch half circuit are connected respectively to the feedback input and complementary feedback input of the first slave latch half circuit,   the data output and the complementary data output of the first slave latch half circuit serve respectively as the first data output and the first complementary data output of the slave latch, and   the data output and the complementary data output of the second slave latch half circuit serve respectively as the second data output and the second complementary data output of the slave latch.   
   
   
       7 . The design structure of  claim 6 , wherein each of the slave latch half circuits is comprised of:
 a first NOR gate having a first input coupled to the first complementary data input and a second input coupled to the second complementary data input;   a second NOR gate having a first input coupled to the first data input and a second input coupled to the second data input;   a first output transistor having one drain-source region coupled to a source of high potential and the other drain-source region coupled to the data output;   a second output transistor having one drain-source region coupled to the data output and the other drain-source region coupled to ground potential;   a third output transistor having one drain-source region coupled to the source of high potential and the second drain-source region coupled to the complementary data output;   a fourth output transistor having one drain-source region coupled to the first complementary output and the other drain-source region coupled to ground potential;   a first series string of three transistors connected in with parallel with the first output transistor, the first string including a first transistor having one drain-source region coupled to the source of high potential, a second transistor having one drain-source region coupled to the other drain-source region of the first transistor, and a third transistor having one drain-source region coupled to the other drain-source region of the second transistor and the other drain-source region coupled to the data output;   a second series string of three transistors connected in with parallel with the second output transistor, the second string including a first transistor having one drain-source region coupled to the data output, a second transistor having one drain-source region coupled to the other drain-source region of the first transistor, and a third transistor having one drain-source region coupled to the other drain-source region of the second transistor and the other drain-source region coupled to ground potential;   a third series string of three transistors connected in with parallel with the third output transistor, the third string including a first transistor having one drain-source region coupled to the source of high potential, a second   transistor having one drain-source region coupled to the other drain-source region of the first transistor, and a third transistor having one drain-source region coupled to the other drain-source region of the second transistor and the other drain-source region coupled to the complementary data output; and   a fourth series string of three transistors connected in with parallel with the fourth output transistor, the fourth string including a first transistor having one drain-source region coupled to the complementary data output, a second transistor having one drain-source region coupled to the other drain-source region of the first transistor, and a third transistor having one drain-source region coupled to the other drain-source region of the second transistor and the other drain-source region coupled to ground potential,   wherein   the first data input is coupled to the gates of third output transistor and the first transistor in the fourth series string,   the first complementary data input is coupled to the gates of the first output transistor and the first transistor in the second series string,   output of the first NOR gate is coupled to the gates of the fourth output transistor and the third transistor in the third series string,   output of the second NOR gate is coupled to the gates of the second output transistor and the third transistor in the second series string,   the data output is coupled to the gates of the second transistor in the third series string and the third transistor in the fourth series string,   the complementary output is coupled to the gates of the second transistor in the first series string and the third transistor in the second series string,   the feedback input is coupled to the gates of the first transistor in the third series string and the second transistor in the fourth series string, and   the complementary feedback input is coupled to the gates of the first transistor in the first series string and the second transistor in the second series string.   
   
   
       8 . The design structure of  claim 1 , wherein the programmable phase frequency divider circuit is implemented in CMOS technology. 
   
   
       9 . The design structure of  claim 1 , wherein the design structure comprises a netlist which describes the programmable phase frequency divider circuit. 
   
   
       10 . The design structure of  claim 1 , wherein the design structure resides on the machine readable medium as a data format used for the exchange of layout data for integrated circuits. 
   
   
       11 . The design structure of  claim 1 , wherein the design structure includes at least one of test data files, characterization data, verification data and design specifications.