Semiconductor device and manufacturing method therefor

Abstract

A semiconductor device having an active element and an MIM capacitor and a structure capable of reducing the number of the manufacturing steps thereof and a manufacturing method therefor are provided. The semiconductor device has a structure that the active element having an ohmic electrode and the MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode are formed on a semiconductor substrate, wherein the lower electrode and ohmic electrode have the same structure. In an MMIC 100 in which an FET as an active element and the MIM capacitor are formed on a GaAs substrate 10 , for example, a source electrode 16 a and a drain electrode 16 b , which are ohmic electrodes of the FET, are manufactured simultaneously with a lower electrode 16 c of the MIM capacitor. Here the electrodes are formed with the same metal.

1 . A semiconductor device comprising:
 an active element having an ohmic electrode formed on a semiconductor substrate; and   a MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode provided on the semiconductor substrate;   wherein the lower electrode has substantially the same structure as that of the ohmic electrode.   
   
   
       2 . The semiconductor device according to  claim 1 , wherein the active element is a field effect transistor and the ohmic electrode is a source electrode or a drain electrode. 
   
   
       3 . The semiconductor device according to  claim 1 , wherein;
 the semiconductor substrate is a semi-insulating semiconductor substrate,   the active element is a PIN diode including   an n-type semiconductor layer formed on the substrate,   a first ohmic electrode formed on the n-type semiconductor layer,   a p-type semiconductor layer formed on the substrate, and   a second ohmic electrode formed On the p-type semiconductor layer,   wherein the lower electrode has substantially the same structure as that of the first ohmic electrode or the second ohmic electrode.   
   
   
       4 . The semiconductor device according to  claim 1 , wherein the lower electrode has a structure that the first ohmic electrode and the second ohmic electrode are laminated. 
   
   
       5 . The semiconductor device according to  claim 1 , wherein an insulating film is formed between the substrate and the lower electrode. 
   
   
       6 . A method for manufacturing a semiconductor device, the method comprising:
 forming an active element having an ohmic electrode, and   forming an MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode on a semiconductor substrate,   wherein the lower electrode is manufactured simultaneously with the ohmic electrode.   
   
   
       7 . The method for manufacturing a semiconductor device according to  claim 6 , wherein the lower electrode and the ohmic electrode are formed by laminating a plurality of metal layers, being subject to heat-treating at 400° C. or lower and alloying the laminating metal layers. 
   
   
       8 . The method for manufacturing a semiconductor device according to  claim 7 , wherein the active element is a field effect transistor and the ohmic electrode is a source electrode or a drain electrode. 
   
   
       9 . The method for manufacturing a semiconductor device according to  claim 7 , wherein;
 the semiconductor substrate is a semi-insulating semiconductor substrate,   the active element is a PIN diode including   an n-type semiconductor layer formed on the substrate,   a first ohmic electrode formed on the n-type semiconductor layer,   a p-type semiconductor layer formed on the substrate, and   a second ohmic electrode formed on the p-type semiconductor layer, and wherein   the lower electrode has substantially the same structure as that of the first ohmic electrode or the second ohmic electrode.   
   
   
       10 . The method for manufacturing a semiconductor device according to  claim 7 ,
 wherein the lower electrode of the MIM capacitor has a two-layer structure composed of an upper layer portion and a lower layer portion and   the lower layer portion of the lower electrode is formed simultaneously with the first ohmic electrode and the upper layer portion of the lower electrode is formed simultaneously with the second ohmic electrode.   
   
   
       11 . The method for manufacturing a semiconductor device having a field effect transistor and an MIM capacitor formed on a semi-insulating semiconductor substrate according to  claim 7 , the method further comprising:
 forming an active layer on a part of the semiconductor substrate;   forming an insulating film in a portion on the active layer excluding a area for forming the source and drain electrodes composing the field effect transistor and a portion of the semiconductor substrate excluding the active layer;   forming a first resist film on the insulating film having openings at portions for forming the source and drain electrode and at a portion for forming the lower electrode of the MIM capacitor;   forming a first metal layer for making ohmic contact with the active layer on the entire surface of the substrate via the first resist film; and   removing the resist film and the first metal film thereon by a lift-off method, thereby forming the source and drain electrodes and the lower electrode of the MIM capacitor.   
   
   
       12 . The method for manufacturing a semiconductor device according to  claim 11 , wherein the semi-insulating semiconductor substrate is a GaAs substrate. 
   
   
       13 . The method for manufacturing a semiconductor device according to  claim 12 , wherein the first metal film is formed with AuGe/Au. 
   
   
       14 . The method for a semiconductor device according to  claim 12 , further comprising:
 forming a second resist film having an opening on a portion of a surface where the gate electrode of the field effect transistor is formed;   forming a second metal film on the entire surface on the substrate via the second resist film,   removing the resist film and the second metal film thereon by a lift-off method, thereby forming the gate electrode;   forming an insulating film to cover a part of the gate electrode, the source electrode and the drain electrode and a surface of the lower electrode of the MIM capacitor,   forming on the insulating film a third resist film having an opening to expose a part of the source and drain electrodes and a part of the insulating film on the lower electrode of the MIM capacitor,   forming a third metal film over an entire surface of the active layer via the third resist film, and   removing the resist film and the third metal film thereon by the lift-off method, thereby forming the upper electrodes of the source and drain electrodes and the upper electrode of the MIM capacitor.   
   
   
       15 . The method for manufacturing a semiconductor device according to  claim 12 , wherein the semi-insulating semiconductor substrate is a GaAs substrate. 
   
   
       16 . The method for manufacturing a semiconductor device according to  claim 15 , wherein the second metal film is formed with AuGe/Au. 
   
   
       17 . The method for manufacturing a semiconductor device according to  claim 15 , wherein the third metal film is formed with Ti/Pt/Au. 
   
   
       18 . The method for manufacturing a semiconductor device according to  claim 12 , wherein the insulating film is formed with SiN.