Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees

Abstract

Design structure for a clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

1 . A design structure embodied in a computer readable medium for performing a method of integrating a clock distribution network and a logic design in an integrated circuit, the clock distribution network having a number of distribution levels from a clock source and a plurality of logic leaf connection nodes, each distribution level including at least one distribution segment, the design structure comprising:
 a means for providing a logic design having a plurality of clocked logic elements;   a means for determining a desired load value for each of the plurality of logic leaf connection nodes;   a means for grouping one or more of said plurality of clocked logic elements together in a corresponding respective one of a plurality of register structures, each of said plurality of clocked logic elements being grouped in one of said plurality of register structures, each of said plurality of register structures having a load on said clock distribution network that is substantially the same as said desired load value; and   a means for assigning each of said plurality of register structures to a corresponding respective one of said plurality of logic leaf connection nodes.   
   
   
       2 . The design structure of  claim 1 , wherein the design structure comprises a netlist. 
   
   
       3 . The design structure of  claim 1 , wherein the design structure resides on a storage medium as a data format used for the exchange of layout data of integrated circuits. 
   
   
       4 . The design structure of  claim 1 , wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications. 
   
   
       5 . A design structure embodied in a machine readable medium for performing a method of integrating a clock distribution network and a logic design in an integrated circuit, the clock distribution network having a number of distribution levels from a clock source and a plurality of logic leaf connection nodes, each distribution level including at least one distribution segment, the design structure comprising:
 a means for providing a logic design having a plurality of clocked logic elements;   a means for determining a desired load value for each of the plurality of logic leaf connection nodes;   a means for grouping one or more of said plurality of clocked logic elements together in a corresponding respective one of a plurality of register structures, each of said plurality of clocked logic elements being grouped in one of said plurality of register structures, each of said plurality of register structures having a load on said clock distribution network that is substantially the same as said desired load value;   a means for connecting each of said plurality of register structures to a corresponding respective one of said plurality of logic leaf connection nodes;   a means for connecting a dummy register to a corresponding respective one of said plurality of logic leaf connection nodes that is not connected to one of said plurality of registers, said dummy register having a load on said clock distribution network that is substantially the same as said desired load value;   a means for connecting a tuning element to a corresponding respective one of said plurality of logic leaf connection nodes that is not connected to one of said plurality of register structures; and   a means for ensuring that all of said plurality of logic leaf connection nodes have a load that is substantially the same as said desired load value.   
   
   
       6 . The design structure of  claim 5 , wherein the design structure comprises a netlist. 
   
   
       7 . The design structure of  claim 5 , wherein the design structure resides on a storage medium as a data format used for the exchange of layout data of integrated circuits. 
   
   
       8 . The design structure of  claim 5 , wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.